"COMPAS; RESPIN; Scan Chain; Testability"@en . . "Neuveden" . . "Nov\u00E1k, Ond\u0159ej" . . . "Komprese testovac\u00EDch vzork\u016F pro obvody s RESPIN architekturou"@cs . "Zahr\u00E1dka, Ji\u0159\u00ED" . . "2005-05-22+02:00"^^ . "83-919289-9-3" . . . "\u010Cl\u00E1nek p\u0159edstavuje kompaktn\u00ED metodu s kombinac\u00ED kompresn\u00ED techniky, kter\u00E1 p\u0159ipravuje komprimovan\u00E9 testovac\u00ED vzorky pro RESPIN architekturu. RESPIN architektura je kompatibiln\u00ED se standardem IEEE 1500."@cs . . "The test pattern compaction method combined with test input data compression technique for the RESPIN architecture is presented. RESPIN architecture is compatible with the IEEE 1500 standard and can be implemented in complex SoCs." . . "Informal Digest of Papers of the 10th IEEE European Test Symposium" . "546462" . "6"^^ . "The test pattern compaction method combined with test input data compression technique for the RESPIN architecture is presented. RESPIN architecture is compatible with the IEEE 1500 standard and can be implemented in complex SoCs."@en . "141-146" . "Test Pattern Compression for Circuits with the RESPIN Architecture"@en . "Tallinn, Estonia" . . "Komprese testovac\u00EDch vzork\u016F pro obvody s RESPIN architekturou"@cs . "RIV/46747885:24220/05:00000136" . "Tallinn, Estonia" . "Test Pattern Compression for Circuits with the RESPIN Architecture"@en . . "2"^^ . . . . "Test Pattern Compression for Circuits with the RESPIN Architecture" . "RIV/46747885:24220/05:00000136!RIV06-GA0-24220___" . "[13B3CCF10B13]" . "24220" . "P(GA102/04/2137)" . . . "2"^^ . "Test Pattern Compression for Circuits with the RESPIN Architecture" . . .