"3"^^ . . . "0"^^ . "Hardware Overhead of Boundary Scan and RAS Design Methodologies"@en . "0"^^ . . "4"^^ . "2"^^ . . "%22Low power design; BS; JTAG; RAS; diagnostics; test; BIST%22"@en . . "80-214-2094-4" . "Bourdeu d'Aguerre, Philippe" . "RIV/46747885:24220/02:00000002!RIV/2003/GA0/242203/N" . . "In this paper we present results of our experiments with integrated circuit BISTE. We have compared the hardware overhead of the BS diagnostic equipment with the RAS design. We have built the RAS diagnostic equipment with the same controlling circuitry aFurther area reduction can be obtained by using built-in TPG on chip. These generators spare the memory for storing the test vectors. We have found that when using this kind of test pattern generators the total area devoted for diagnostics is the lowest" . . "P(GA102/01/0566), Z(MSM 242200002)" . "Pl\u00EDva, Zden\u011Bk" . "2002-04-17+02:00"^^ . . "Hardware Overhead of Boundary Scan and RAS Design Methodologies" . "In this paper we present results of our experiments with integrated circuit BISTE. We have compared the hardware overhead of the BS diagnostic equipment with the RAS design. We have built the RAS diagnostic equipment with the same controlling circuitry aFurther area reduction can be obtained by using built-in TPG on chip. These generators spare the memory for storing the test vectors. We have found that when using this kind of test pattern generators the total area devoted for diagnostics is the lowest"@en . "Nov\u00E1k, Ond\u0159ej" . "Hardware Overhead of Boundary Scan and RAS Design Methodologies"@en . . . . "RIV/46747885:24220/02:00000002" . . . "647400" . "Vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Brn\u011B. Fakulta informa\u010Dn\u00EDch technologi\u00ED" . . . . . . "Proceedings of the 5th International workshop IEEE DDECS2002" . "24220" . "[B8551DFCD32D]" . . . "Brno, Czech" . . . "Brno, Czech" . "36-43" . "Hardware Overhead of Boundary Scan and RAS Design Methodologies" . .