. "RIV/46747885:24220/00:00000031" . "Nov\u00E1k, Ondrej" . "[A9CE58409CC0]" . "An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain"@en . "3"^^ . "Nov\u00E1k, Ondrej" . . "205" . . "4"^^ . "Proc. of Design and Diagnostics of Electronics Circuits and System Workshop" . "Slovensk\u00E1 akad\u00E9mia vied" . . . "24220" . "An Efficient Deterministic test Pattern Compaction Scheme Using Modified IC Scan Chain" . "RIV/46747885:24220/00:00000031!RIV/2001/MSM/242201/N" . . . "720736" . "80-968320-" . . . "Optimised Hardware Test Pattern Generator for BIST"@en . . "IC design"@en . "3"^^ . "Optimised Hardware Test Pattern Generator for BIST"@en . "Optimised Hardware Test Pattern Generator for BIST" . "P(VS96006), Z(MSM 242200002)" . . . "Optimised Hardware Test Pattern Generator for BIST" . . "Slovensko" . .