"RIV/00216305:26230/14:PU112083!RIV15-GA0-26230___" . "1401" . "Mr\u00E1zek, Vojt\u011Bch" . . "http://dx.doi.org/10.1109/ICES.2014.7008716" . "The aim of this paper is to introduce a new acceleratordeveloped to address the problem of evolutionary synthesisof digital circuits at transistor level. The proposed accelerator,based on recently introduced Xilinx Zynq platform, consists ofa discrete simulator implemented in programmable logic and anevolutionary algorithm running on a tightly coupled embeddedARM processor. The discrete simulator was introduced in order toachieve a good trade-off between the precision and performanceof the simulation of transistor-level circuits. The simulator isimplemented using the concept of virtual reconfigurable circuitand operates on multiple logic levels which enables to evaluate thebehavior of candidate transistor-level circuits at a reasonable levelof detail. In this work, the concept of virtual reconfigurable circuitwas extended to enable bidirectional data flow which representsthe basic feature of transistor level circuits. According to theexperimental evaluation, the proposed architecture speed"@en . "Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform"@en . . "10.1109/ICES.2014.7008716" . . "2014-12-09+01:00"^^ . "978-1-4799-4480-4" . "2014 IEEE International Conference on Evolvable Systems Proceedings" . "The aim of this paper is to introduce a new acceleratordeveloped to address the problem of evolutionary synthesisof digital circuits at transistor level. The proposed accelerator,based on recently introduced Xilinx Zynq platform, consists ofa discrete simulator implemented in programmable logic and anevolutionary algorithm running on a tightly coupled embeddedARM processor. The discrete simulator was introduced in order toachieve a good trade-off between the precision and performanceof the simulation of transistor-level circuits. The simulator isimplemented using the concept of virtual reconfigurable circuitand operates on multiple logic levels which enables to evaluate thebehavior of candidate transistor-level circuits at a reasonable levelof detail. In this work, the concept of virtual reconfigurable circuitwas extended to enable bidirectional data flow which representsthe basic feature of transistor level circuits. According to theexperimental evaluation, the proposed architecture speed" . . . . . "Institute of Electrical and Electronics Engineers" . "Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform"@en . . . "[24681F5E9B60]" . . "Orlando" . . "2"^^ . . "Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform" . "2"^^ . "26230" . . "RIV/00216305:26230/14:PU112083" . . "P(GA14-04197S)" . "Va\u0161\u00ED\u010Dek, Zden\u011Bk" . "Acceleration of Transistor-Level Evolution using Xilinx Zynq Platform" . . "Xilinx Zynq, transistor-level evolution, evolutionary design, combinational circuit"@en . "Piscataway" . . . . "8"^^ .