"P(ED1.1.00/02.0070), S, Z(MSM0021630528)" . "Proceedings of the 2013 International Conference on Field Programmable Technology" . . "3"^^ . . "NFA Reduction for Regular Expressions Matching Using FPGA" . . . "4"^^ . . "RIV/00216305:26230/13:PU107071!RIV14-MSM-26230___" . . "NFA Reduction for Regular Expressions Matching Using FPGA" . "91786" . . "NFA Reduction for Regular Expressions Matching Using FPGA"@en . "RIV/00216305:26230/13:PU107071" . . . "2013-12-09+01:00"^^ . "IEEE Computer Society" . . . . . . . "NFA Reduction for Regular Expressions Matching Using FPGA"@en . . . "978-1-4799-2199-7" . . "Kyoto" . "Kyoto" . . . "[16775E5DBF8D]" . . "Ko\u0159enek, Jan" . "Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources. In this paper, we investigate applicability of NFA reduction techniques - a formal aparatus to reduce the number of states and transitions in NFA prior to its mapping into FPGA. The paper presents several NFA reduction techniques, each with a different reduction power and time complexity. The evaluation utilizes regular expressions from Snort and L7 decoder. The best NFA reduction algorithms achieve more than 66% reduction in the number of states for a Snort ftp module. Such a reduction translates directly into 66% LUT and FF saving in the FPGA."@en . "\u017D\u00E1dn\u00EDk, Martin" . . "3"^^ . . "Ko\u0161a\u0159, Vlastimil" . "FPGA, NFA, Reduction, Regular expressions matching"@en . "Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources. In this paper, we investigate applicability of NFA reduction techniques - a formal aparatus to reduce the number of states and transitions in NFA prior to its mapping into FPGA. The paper presents several NFA reduction techniques, each with a different reduction power and time complexity. The evaluation utilizes regular expressions from Snort and L7 decoder. The best NFA reduction algorithms achieve more than 66% reduction in the number of states for a Snort ftp module. Such a reduction translates directly into 66% LUT and FF saving in the FPGA." . "26230" .