"DE - Spolkov\u00E1 republika N\u011Bmecko" . . . . . . "[21C056AB1F5A]" . "Kajan, Michal" . "7261" . "3"^^ . . . . "Leng\u00E1l, Ond\u0159ej" . "\u0160imkov\u00E1, Marcela" . . . . . "HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware"@en . . "Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In this paper we present HAVEN, a freely available open functional verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification runs. HAVEN takes advantage of the inherent parallelism of hardware systems and moves the verified system together with transaction-based interface components of the functional verification environment from software into an FPGA. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM), assertion-based verification, and also provides adequate debugging visibility, making its application range quite large. Our experiment" . "Kajan, Michal" . "Lecture Notes in Computer Science" . . "3"^^ . . "HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware" . . . "138678" . . "functional verification, testbench, SystemVerilog, hardware acceleration, FPGA"@en . "RIV/00216305:26230/12:PU96138" . "RIV/00216305:26230/12:PU96138!RIV13-GA0-26230___" . "HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware"@en . . "0302-9743" . . . "HAVEN: An Open Framework for FPGA-Accelerated Functional Verification of Hardware" . "26230" . "Functional verification is a widespread technique to check whether a hardware system satisfies a given correctness specification. As the complexity of modern hardware systems rises rapidly, it is a challenging task to find appropriate techniques for acceleration of this process. In this paper we present HAVEN, a freely available open functional verification framework that exploits the field-programmable gate array (FPGA) technology for cycle-accurate acceleration of simulation-based verification runs. HAVEN takes advantage of the inherent parallelism of hardware systems and moves the verified system together with transaction-based interface components of the functional verification environment from software into an FPGA. The presented framework is written in SystemVerilog and complies with the principles of functional verification methodologies (OVM, UVM), assertion-based verification, and also provides adequate debugging visibility, making its application range quite large. Our experiment"@en . "P(7H10013), P(GAP103/10/0306), P(OC10009), S, Z(MSM0021630528)" . "2012" . "7"^^ . . "\u0160imkov\u00E1, Marcela" . .