"RIV/00216305:26230/11:PU96100!RIV12-MSM-26230___" . . "AX32 Low Power Embedded Video Enabled System Using FPGA" . "Chania" . . "Chania" . . . "978-0-7695-4529-5" . "RIV/00216305:26230/11:PU96100" . "Kor\u010Dek, Pavol" . . . . . . . "Zem\u010D\u00EDk, Pavel" . . . "6"^^ . "\u0160ustek, Ji\u0159\u00ED" . "6"^^ . "2"^^ . . "\u0160irok\u00FD, V\u00EDt" . . "Mar\u0161\u00EDk, Luk\u00E1\u0161" . . . . "The contribution presents an architecture for embedded video and signal processing system. The architecture is based on embedded microcomputer with ARM-based CPU and FPGA on the AX32 platform. While the CPU is necessary and integral part of the system, the signal and video processing tasks are %22offloaded%22 to the FPGA in order to save computational power and energy. The target application is in standalone traffic monitoring systems with or without video processing and embedded sensory systems, e.g. in robots. Power consumption is critical as the applications are intended with battery power and also because in some applications, hermetic packaging not allowing heating through e.g. flow of air must be used. The contribution presents a concept of the system, the video and signal processing approach, and draws some conclusions." . "Fu\u010D\u00EDk, Otto" . . "AX32 Low Power Embedded Video Enabled System Using FPGA" . "AX32 Low Power Embedded Video Enabled System Using FPGA"@en . "AX32 platform, embedded system, low power, video/image processing, radar signal processing"@en . "[53E350E0610F]" . "Proceedings of the 21th Conference on Field Programmable Logic and Applications Workshop" . "Kor\u010Dek, Pavol" . "187705" . "26230" . "Institute of Electrical and Electronics Engineers" . . "AX32 Low Power Embedded Video Enabled System Using FPGA"@en . . . . . . . . "P(7H10011), P(7H10013), S, Z(MSM0021630528)" . "2011-09-05+02:00"^^ . "The contribution presents an architecture for embedded video and signal processing system. The architecture is based on embedded microcomputer with ARM-based CPU and FPGA on the AX32 platform. While the CPU is necessary and integral part of the system, the signal and video processing tasks are %22offloaded%22 to the FPGA in order to save computational power and energy. The target application is in standalone traffic monitoring systems with or without video processing and embedded sensory systems, e.g. in robots. Power consumption is critical as the applications are intended with battery power and also because in some applications, hermetic packaging not allowing heating through e.g. flow of air must be used. The contribution presents a concept of the system, the video and signal processing approach, and draws some conclusions."@en . .