"Proceedings of the 16th Conference Student EEICT 2010 Volume 5" . . "ASIP, retargetable compilers, ADL, Lissom, ISAC"@en . "264224" . . . "Instruction Selection Patterns Extraction from Architecture Specification Language ISAC"@en . . . "P\u0159ikryl, Zden\u011Bk" . . "Instruction Selection Patterns Extraction from Architecture Specification Language ISAC" . . . "Hru\u0161ka, Tom\u00E1\u0161" . "[CF025437A632]" . . "5"^^ . "Vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Brn\u011B. Fakulta informa\u010Dn\u00EDch technologi\u00ED" . . "978-80-214-4080-7" . "This paper deals with retargetable compiler generation. After a short introduction to application specific instruction set processor design, ISAC architecture description language is briefly described. In the second part of this paper, algorithm that transforms ISAC architecture model to a model usable for compiler backend generation is described. A tool that performs this translation was implemented and tested on MIPS and ARM architecture models. Compiler backend generation from the compiler generation model is still work-in-progress and is not presented here." . . "Hus\u00E1r, Adam" . . . . . "Brno" . . "RIV/00216305:26230/10:PU89539!RIV12-MPO-26230___" . . "FEKT VUT v Brn\u011B" . "P(FR-TI1/038), P(FT-TA3/128), P(GD102/09/H042), S, Z(MSM0021630528)" . "Instruction Selection Patterns Extraction from Architecture Specification Language ISAC" . "26230" . . . "Instruction Selection Patterns Extraction from Architecture Specification Language ISAC"@en . . "Trma\u010D, Miloslav" . "RIV/00216305:26230/10:PU89539" . . "4"^^ . "2010-04-29+02:00"^^ . . . . . "4"^^ . "This paper deals with retargetable compiler generation. After a short introduction to application specific instruction set processor design, ISAC architecture description language is briefly described. In the second part of this paper, algorithm that transforms ISAC architecture model to a model usable for compiler backend generation is described. A tool that performs this translation was implemented and tested on MIPS and ARM architecture models. Compiler backend generation from the compiler generation model is still work-in-progress and is not presented here."@en . .