. "P(GA102/07/0850), Z(MSM0021630528)" . . "26230" . . . "Hardware Accelerator for Evolutionary Image Filters Design"@en . . "The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44"@en . . . . "Sekanina, Luk\u00E1\u0161" . . "The EHWFILTER accelerator was developed in order to accelerate image filter evolution in hardware. It can automatically create a filter (e.g., to suppress shot noise) when noised image and uncorrupted original image are provided. The accelerator is implemented on the COMBO6X card equipped with Virtex II Pro 2VP50ff1517 FPGA. It consists of genetic unit, fitness unit and the so-called virtual reconfigurable circuit (VRC) which is utilized to evaluate candidate filters. Every image filter is considered as a digital circuit of nine 8-bit inputs and a single 8-bit output, which processes grayscale (8-bits/pixel) images. Training images are stored in external SRAM memories. The search algorithm is based on Cartesian Genetic Programming operating over 4x8 programmable elements, population size of 8 individuals, and 1 mutation/chromosome. This setting is default but can be changed. The accelerator is connected with PC using PCI bus. The system requires approx. 10 sec to produce a filter which is 44" . "EHWFILTER" . "Akceler\u00E1tor je implementov\u00E1n na kart\u011B COMBO6X vybaven\u00E9 FPGA Virtex II Pro 2VP50ff1517 obsahuj\u00EDc\u00ED procesor PowerPC. Intern\u011B procesor pracuje na 300 MHz, podp\u016Frn\u00E1 logika na 150 MHz. Ostatn\u00ED komponenty akceler\u00E1toru (virtu\u00E1ln\u00ED rekonfigurovateln" . . "Hardware Accelerator for Evolutionary Image Filters Design"@en . . "accelerator, FPGA, Combo6X, evolutionary algorithm, image filter"@en . . "Va\u0161\u00ED\u010Dek, Zden\u011Bk" . . "RIV/00216305:26230/09:PR24513!RIV10-MSM-26230___" . "316850" . "Hardware Accelerator for Evolutionary Image Filters Design" . . "\u00DAstav po\u010D\u00EDta\u010Dov\u00FDch syst\u00E9m\u016F, Fakulta informa\u010Dn\u00EDch technologi\u00ED VUT v Brn\u011B, Bo\u017Eet\u011Bchova 2, 612 66 Brno, http://www.fit.vutbr.cz/units/UPSY/" . . . "2"^^ . "Cena z\u00E1vis\u00ED na po\u010Dtu odeb\u00EDran\u00FDch kus\u016F." . "2"^^ . . . . "RIV/00216305:26230/09:PR24513" . "[B6D3FB839E2C]" . . "Hardware Accelerator for Evolutionary Image Filters Design" . . . .