"IEEE Computer Society" . "6"^^ . "369394" . . "Interconnection system, PCI Express, FPGA
"@en . "Z(MSM0021630528), Z(MSM6383917201)" . . "3"^^ . "GICS: Generic Interconnection System"@en . "978-1-4244-1961-6" . . "3"^^ . . "GICS: Generic Interconnection System" . . "[35CABB032D02]" . . . "Rozd\u011Blen\u00ED aplikace mezi konven\u010Dn\u00ED procesor a akcelera\u010Dn\u00ED kartu s FPGA \u010Dipy se uk\u00E1zalo jako vhodn\u00FD zp\u016Fsob pro akceleraci v\u00FDpo\u010Detn\u011B n\u00E1ro\u010Dn\u00FDch \u00FAloh. V t\u011Bchto aplikac\u00EDch, mus\u00ED vyvoj\u00E1\u0159 obvykle implementovat propojovac\u00ED syst\u00E9m mezi komponentami um\u00EDst\u011Bn\u00FDmi v FPGA a syst\u00E9movou sb\u011Brnic\u00ED. Tento \u00FAkol je v\u0161ak \u010Dasto komplikov\u00E1n r\u016Fzn\u00FDmi po\u017Eadavky ze strany u\u017Eivatelsk\u00FDch komponent nap\u0159. na propustnost, latenci \u010Dtec\u00EDch operac\u00ED, pot\u0159eba DMA p\u0159enos\u016F apod. C\u00EDlem t\u00E9to pr\u00E1ce je uk\u00E1zat nov\u00FD p\u0159\u00EDstup pro implementaci propojovac\u00EDho syst\u00E9mu a umo\u017Enit v\u00FDvoj\u00E1\u0159i se soust\u0159edit na v\u00FDvoj c\u00EDlov\u00E9 aplikace. Navrhovan\u00FD propojovac\u00ED syst\u00E9m je zalo\u017Een na stromov\u00E9 architektu\u0159e, eliminuje citlivost na vzd\u00E1lenost, podporuje p\u0159ipojen\u00ED komponent s r\u016Fzn\u00FDmi po\u017Eadavky na propustnost, podporuje model rozd\u011Blen\u00FDch transakc\u00ED a mnoho dal\u0161\u00EDch vlastnost\u00ED. Navrhovan\u00FD syst\u00E9m je implementov\u00E1n a ohodnocen na \u010Dipech s technologi\u00ED Virtex 5.
"@cs . . . . "M\u00E1lek, Tom\u00E1\u0161" . . . . . "Heidelberg, Germany" . "GICS: Generic Interconnection System" . "RIV/00216305:26230/08:PU78052" . . "GICS: Generick\u00FD propojovac\u00ED syst\u00E9m"@cs . "RIV/00216305:26230/08:PU78052!RIV09-MSM-26230___" . "2008-09-08+02:00"^^ . "2008 International Conference on Field Programmable Logic and Applications" . "The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application.  The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t"@en . "GICS: Generic Interconnection System"@en . . . "Ko\u0159enek, Jan" . "Mart\u00EDnek, Tom\u00E1\u0161" . "Heidelberg" . . "The division of an application between a conventional processor and an acceleration card with FPGA chips has been proved as a suitable way for an acceleration of computationally intensive tasks. In such applications, the designer usually has to implement an interconnection between components placed in FPGA and the host system bus. This task is often complicated by different requirements of user components for throughput, latency of reading operations, need for DMA transfers etc. The objective of this work is to show a new approach for implementation of interconnection systems and to enable the designer to focus on the development of the target application.  The proposed interconnection system is based on tree topology. The system eliminates the sensitivity of wide buses to the distance, supports the connection of components with different requirements for throughput, supports split transaction model and many other features. The proposed system is implemented and evaluated on chips with Virtex 5 t" . . "26230" . "GICS: Generick\u00FD propojovac\u00ED syst\u00E9m"@cs .