"P(GD102/05/H050), Z(MSM0021630528)" . . . "978-0-7695-3277-6" . . "Digital Systems Architectures Based on On-line Checkers"@en . . . "3"^^ . "RIV/00216305:26230/08:PU76713!RIV10-MSM-26230___" . "RIV/00216305:26230/08:PU76713" . . "3"^^ . . "11th EUROMICRO Conference on Digital System Design DSD 2008" . . . "Parma" . "26230" . . "Parma" . "Fault Tolerant Systems, simple circuit, checker, FPGA, on-line testing, ,protocols"@en . . "Kot\u00E1sek, Zden\u011Bk" . . "2008-09-03+02:00"^^ . "Straka, Martin" . "Digital Systems Architectures Based on On-line Checkers" . "Digital Systems Architectures Based on On-line Checkers"@en . . . . "Digital Systems Architectures Based on On-line Checkers" . "Winter, Jan" . "363627" . . . "8"^^ . . . . . "In this paper, we present a methodology for generating
VHDL descriptions of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how a
checker for more complex structures can be developed. We
describe the possibilities of utilizing this approach in the design
of Fault Tolerant Systems (FTS). Experimental results
in terms of FPGA resources needed to synthesize different
types of checkers are presented." . . . "[90CCA7321A37]" . "In this paper, we present a methodology for generating
VHDL descriptions of hardware checkers is presented. It is
shown how the methodology can be used to generate on-line
checkers of communication protocols, counters, decoders,
registers, comparators, etc. It is also demonstrated how a
checker for more complex structures can be developed. We
describe the possibilities of utilizing this approach in the design
of Fault Tolerant Systems (FTS). Experimental results
in terms of FPGA resources needed to synthesize different
types of checkers are presented."@en . . "IEEE Computer Society" .