. "Vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Brn\u011B. Fakulta informa\u010Dn\u00EDch technologi\u00ED" . "Z(MSM0021630528)" . "[741145F2D6FD]" . . "Anal\u00FDza a zlep\u0161en\u00ED testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F na \u00FArovni meziregistrov\u00FDch p\u0159enos\u016F" . "Anal\u00FDza a zlep\u0161en\u00ED testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F na \u00FArovni meziregistrov\u00FDch p\u0159enos\u016F"@cs . . . . . "testability analysis, digital circuit, data path, graph algorithm, diagnostics, hierarchical test, design for testability, testability, transparency, register-transfer level"@en . "Pr\u00E1ce se v\u011Bnuje problematice anal\u00FDzy testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F popsan\u00FDch na \u00FArovni megistrov\u00FDch p\u0159enos\u016F. V pr\u00E1ci je uk\u00E1z\u00E1no, \u017Ee je-li ka\u017Ed\u00FD modul z knihovny modul\u016F tvo\u0159\u00EDc\u00EDch strukturu dan\u00E9ho obvodu vybaven krom\u011B
informace vzta\u017Een\u00E9 k n\u00E1vrhu i vhodnou diagnostickou informac\u00ED, pak je mo\u017Eno doc\u00EDlit p\u0159esn\u011Bj\u0161\u00EDho ohodnocen\u00ED testovatelnosti dan\u00E9ho obvodu. K popisu zm\u00EDn\u011Bn\u00E9 informace je vyu\u017Eit matematick\u00FD model zalo\u017Een\u00FD na tzv. koncepci virtu\u00E1ln\u00EDch port\u016F. Samotn\u00E1 metoda anal\u00FDzy testovatelnosti je zalo\u017Eena na anal\u00FDze dvou orientovan\u00FDch graf\u016F p\u0159edstavuj\u00EDc\u00EDch model toku diagnostick\u00FDch dat dan\u00FDm obvodem. Zvl\u00E1\u0161\u0165 je modelov\u00E1n datov\u00FD tok vzork\u016F a odezev. V z\u00E1v\u011Bru pr\u00E1ce jsou
nast\u00EDn\u011Bny mo\u017Enosti uplatn\u011Bn\u00ED navr\u017Een\u00E9 metody v praxi a prezentov\u00E1ny experiment\u00E1ln\u00ED v\u00FDsledky dosa\u017Een\u00E9 aplikac\u00ED t\u00E9to metody v n\u011Bkolika oblastech souvisej\u00EDc\u00EDch s automatizac\u00ED n\u00E1vrhu pro snadnou testovatelnost."@cs . . "187"^^ . . . "Strnadel, Josef" . . . "1"^^ . . . "NEUVEDEN" . "Pr\u00E1ce se v\u011Bnuje problematice anal\u00FDzy testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F popsan\u00FDch na \u00FArovni megistrov\u00FDch p\u0159enos\u016F. V pr\u00E1ci je uk\u00E1z\u00E1no, \u017Ee je-li ka\u017Ed\u00FD modul z knihovny modul\u016F tvo\u0159\u00EDc\u00EDch strukturu dan\u00E9ho obvodu vybaven krom\u011B
informace vzta\u017Een\u00E9 k n\u00E1vrhu i vhodnou diagnostickou informac\u00ED, pak je mo\u017Eno doc\u00EDlit p\u0159esn\u011Bj\u0161\u00EDho ohodnocen\u00ED testovatelnosti dan\u00E9ho obvodu. K popisu zm\u00EDn\u011Bn\u00E9 informace je vyu\u017Eit matematick\u00FD model zalo\u017Een\u00FD na tzv. koncepci virtu\u00E1ln\u00EDch port\u016F. Samotn\u00E1 metoda anal\u00FDzy testovatelnosti je zalo\u017Eena na anal\u00FDze dvou orientovan\u00FDch graf\u016F p\u0159edstavuj\u00EDc\u00EDch model toku diagnostick\u00FDch dat dan\u00FDm obvodem. Zvl\u00E1\u0161\u0165 je modelov\u00E1n datov\u00FD tok vzork\u016F a odezev. V z\u00E1v\u011Bru pr\u00E1ce jsou
nast\u00EDn\u011Bny mo\u017Enosti uplatn\u011Bn\u00ED navr\u017Een\u00E9 metody v praxi a prezentov\u00E1ny experiment\u00E1ln\u00ED v\u00FDsledky dosa\u017Een\u00E9 aplikac\u00ED t\u00E9to metody v n\u011Bkolika oblastech souvisej\u00EDc\u00EDch s automatizac\u00ED n\u00E1vrhu pro snadnou testovatelnost." . "355996" . . . "Testability Analysis and Improvements of Register-Transfer Level Digital Circuits"@en . "1"^^ . "Brno" . . "RIV/00216305:26230/08:PU76679" . "978-80-214-3599-5" . . . "Testability Analysis and Improvements of Register-Transfer Level Digital Circuits"@en . "Anal\u00FDza a zlep\u0161en\u00ED testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F na \u00FArovni meziregistrov\u00FDch p\u0159enos\u016F"@cs . . "RIV/00216305:26230/08:PU76679!RIV10-MSM-26230___" . "The work deals with problems related to testability analysis method applicable to regis-ter-transfer level digital circuits. It is shown if each module stored in a design library is equipped both with information related to design and information related to testing, then more accurate testability results can be achieved. A mathematical model based on so-called virtual port conception is utilized to describe the information and proposed testability analysis method. The method is based on the idea of searching two special digraphs, each of them modeling transfers of diagnostic data within circuit data path. It is important that transfers of vectors and responses are modeled separately. At the end of the work, possible applications of the method in practise are outlined together with experimental results gained by the method in several areas related to automation of design for testability process."@en . "Anal\u00FDza a zlep\u0161en\u00ED testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F na \u00FArovni meziregistrov\u00FDch p\u0159enos\u016F" . . "26230" . . "Anal\u00FDza a zlep\u0161en\u00ED testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F na \u00FArovni meziregistrov\u00FDch p\u0159enos\u016F" . "187"^^ . .