. . . "Verifying Parametrised Hardware Designs Via Counter Automata"@en . "RIV/00216305:26230/08:PU70924" . "The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of such designs to counter automata and on exploiting the recent advances achieved in the area of their automated formal verification. We have implemented the proposed translation. Using one of the state-of-the-art tools for verification of counter automata, we were then able to verify several non-trivial properties of parametrised VHDL components, including a real-life one."@en . . "IBM Haifa Labs" . . "Z(MSM0021630528), Z(MSM6383917201)" . "The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of such designs to counter automata and on exploiting the recent advances achieved in the area of their automated formal verification. We have implemented the proposed translation. Using one of the state-of-the-art tools for verification of counter automata, we were then able to verify several non-trivial properties of parametrised VHDL components, including a real-life one." . . "Vojnar, Tom\u00E1\u0161" . "Hardware and Software, Verification and Testing" . . "Verifying Parametrised Hardware Designs Via Counter Automata"@en . . . . "Smr\u010Dka, Ale\u0161" . "formal verification, hardware design, counter automaton, VHDL
"@en . . . . "2007-10-23+02:00"^^ . "402554" . "Heidelberg" . "Verifying Parametrised Hardware Designs Via Counter Automata" . . "2"^^ . "RIV/00216305:26230/08:PU70924!RIV10-MSM-26230___" . "2"^^ . "[DF433F1CC75E]" . . . "Springer-Verlag" . . "26230" . . . "18"^^ . "Verifying Parametrised Hardware Designs Via Counter Automata" . "0302-9743" .