"In this paper, the methodology for automated design of checker for
communication protocol testing is presented. Based on the level of
checking, different design strategies can be performed - in the
paper the lowest level is presented. The definition of dedicated
language for the description of possible communication faults is
presented. The core generator is used to produce VHDL code
describing the behaviour of the checker."@en . "2007-08-27+02:00"^^ . . . . "L\u00FCbeck" . "Straka, Martin" . "4"^^ . . . "In this paper, the methodology for automated design of checker for
communication protocol testing is presented. Based on the level of
checking, different design strategies can be performed - in the
paper the lowest level is presented. The definition of dedicated
language for the description of possible communication faults is
presented. The core generator is used to produce VHDL code
describing the behaviour of the checker." . "Lubeck, Germany" . "5"^^ . . . "0-7695-2978-X" . "676-679" . "Online Protocol Testing for FPGA Based Fault Tolerant Systems"@cs . . . "RIV/00216305:26230/07:PU70806!RIV08-MSM-26230___" . "P(GD102/05/H050), Z(MSM0021630528)" . "5"^^ . "Online Protocol Testing for FPGA Based Fault Tolerant Systems"@en . . . "Online Protocol Testing for FPGA Based Fault Tolerant Systems"@cs . . "Ko\u0159enek, Jan" . . "Kot\u00E1sek, Zden\u011Bk" . "RIV/00216305:26230/07:PU70806" . . . "439526" . "Online Protocol Testing for FPGA Based Fault Tolerant Systems"@en . "Online Protocol Testing for FPGA Based Fault Tolerant Systems" . . "Mart\u00EDnek, Tom\u00E1\u0161" . . "Communication Protocol Testing, Fault Tolerant Systems, Checker, FPGA, VHDL"@en . . . . . . "In this paper, the methodology for automated design of checker for
communication protocol testing is presented. Based on the level of
checking, different design strategies can be performed - in the
paper the lowest level is presented. The definition of dedicated
language for the description of possible communication faults is
presented. The core generator is used to produce VHDL code
describing the behaviour of the checker."@cs . "Online Protocol Testing for FPGA Based Fault Tolerant Systems" . "10th EUROMICRO Conference on Digital System Design DSD 2007" . "26230" . "[11E1045FA648]" . . . "IEEE Computer Society" . "Tobola, Ji\u0159\u00ED" .