. . "VHD2CA" . . "VHDL, counter automata, translator, model, formal verification"@en . "455587" . . "1"^^ . "RIV/00216305:26230/07:PR23024!RIV08-MSM-26230___" . . . . "The VHD2CA is the translator of a hardware desing in VHDL to a counter automaton. Some of modern tools for formal verification uses the counter automaton as the formalism for the description of an infinite state space model, thus the translation from VHDL to counter automaton allows the user to formal verify generic (parametric) hardware systems. The translator includes the whole LALR(1) grammar of VHDL'93 language and supports common used constructs."@en . . "1"^^ . . . . "Smr\u010Dka, Ale\u0161" . "Translator of VHDL Design to Counter Automaton" . "Z(MSM0021630528)" . . "Voln\u011B \u0161i\u0159iteln\u00FD software poskytovan\u00FD pod licenc\u00ED GNU GPL." . "http://www.fit.vutbr.cz/~smrcka/projects/vhd2ca/" . "VHD2CA je p\u0159eklada\u010D n\u00E1vrhu po\u010D\u00EDta\u010Dov\u00FDch syst\u00E9m\u016F v jazyku VHDL do \u010D\u00EDta\u010Dov\u00E9ho automatu. N\u011Bkter\u00E9 modern\u00ED n\u00E1stroje pro form\u00E1ln\u00ED verifikaci pou\u017E\u00EDvaj\u00ED \u010D\u00EDta\u010Dov\u00FD automat pro popis nekone\u010Dn\u011B stavov\u00E9ho modelu. Transformace VHDL n\u00E1vrhu do \u010D\u00EDta\u010Dov\u00E9ho automatu umo\u017E\u0148uje form\u00E1ln\u00ED verifikaci obecn\u00FDch (parametrick\u00FDch) po\u010D\u00EDta\u010Dov\u00FDch syst\u00E9m\u016F. P\u0159eklada\u010D zahrnuje celou LALR(1) gramatiku jazyka VHDL'93 a podporuje v\u011Bt\u0161inu pou\u017E\u00EDvan\u00FDch konstrukc\u00ED."@cs . . "P\u0159eklada\u010D VHDL designu do \u010D\u00EDta\u010Dov\u00E9ho automatu"@cs . . "[C36B2838113B]" . . "Translator of VHDL Design to Counter Automaton"@en . "P\u0159eklada\u010D VHDL designu do \u010D\u00EDta\u010Dov\u00E9ho automatu"@cs . . . . "Objektov\u011B orientovan\u00E1 knihovna a program v jazyku Python (verze 2.4 a vy\u0161\u0161\u00ED) s otev\u0159en\u00FDm k\u00F3dem. Program a knihovna je pou\u017Eiteln\u00FD pro v\u0161echny platformy podporuj\u00EDc\u00ED interpret jazyka Python. Rozsah zdrojov\u00FDch k\u00F3d\u016F je cca 9 tis\u00EDc \u0159\u00E1dk\u016F." . "Translator of VHDL Design to Counter Automaton" . . "The VHD2CA is the translator of a hardware desing in VHDL to a counter automaton. Some of modern tools for formal verification uses the counter automaton as the formalism for the description of an infinite state space model, thus the translation from VHDL to counter automaton allows the user to formal verify generic (parametric) hardware systems. The translator includes the whole LALR(1) grammar of VHDL'93 language and supports common used constructs." . "RIV/00216305:26230/07:PR23024" . "Translator of VHDL Design to Counter Automaton"@en . "26230" . . .