"26230" . "Pl\u00E1nov\u00E1n\u00ED testu pro SOC zohled\u0148uj\u00EDc\u00ED p\u0159\u00EDkon energie"@cs . "3"^^ . "\u010Cl\u00E1nek se zab\u00FDv\u00E1 pl\u00E1nov\u00E1n\u00EDm testu pro SOC zohled\u0148uj\u00EDc\u00ED p\u0159\u00EDkon elektrick\u00E9 energie. V p\u0159\u00EDsp\u011Bvku je prezentov\u00E1n p\u0159\u00EDstup zalo\u017Een\u00FD na genetick\u00E9m algoritmu, kter\u00FD pro svoji \u010Dinnost vyu\u017E\u00EDv\u00E1 grafov\u00E9ho modelu TACG. C\u00EDlem popisovan\u00E9 metody je minimalizace \u010Dasu nutn\u00E9ho pro aplikaci testu p\u0159i vylou\u010Den\u00ED v\u0161ech mo\u017En\u00FDch konflikt\u016F zdroj\u016F b\u011Bhem aplikace testu a zaji\u0161t\u011Bn\u00ED, \u017Ee odb\u011Br energie b\u011Bhem testu nep\u0159ekro\u010D\u00ED p\u0159edem stanovenou hranici. Navrhovan\u00E1 metoda byla implementov\u00E1na v jazyce C++ a v \u010Dl\u00E1nku jsou prezentov\u00E1ny i experiment\u00E1ln\u00ED v\u00FDsledky se sadou SOC benchmark\u016F ITC'02."@cs . "[8BB15D44D2C1]" . "RIV/00216305:26230/06:PU66874!RIV07-GA0-26230___" . . "1"^^ . . . "RIV/00216305:26230/06:PU66874" . "\u0160karvada, Jaroslav" . "Test Scheduling for SOC under Power Constraints" . "1"^^ . . . "1-4244-0184-4" . "Praha" . "Prague" . "Pl\u00E1nov\u00E1n\u00ED testu pro SOC zohled\u0148uj\u00EDc\u00ED p\u0159\u00EDkon energie"@cs . . . "P(GA102/04/0737)" . . . . "Test Scheduling for SOC under Power Constraints" . "\u010Cesk\u00E1 technika - nakladatelstv\u00ED \u010CVUT" . . . "91-93" . "test scheduling, power constraint, ,test application conflict graph, genetic algorithm"@en . "2006-04-18+02:00"^^ . . . . . . "Test Scheduling for SOC under Power Constraints"@en . "The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research." . "503536" . . "Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems" . "The paper deals with test scheduling under power constraints for SOC. An approach based on genetic algorithm operating on Test Application Conflict Graph is presented. The main goal of the method is to minimize test application time with considering structural resource allocation conflicts and to ensure that test application schedule does not exceed chip power limits. The proposed method was implemented using C++, experimental results with ITC'02 SOC benchmark suite are presented in the paper together with the perspectives for the future research."@en . "Test Scheduling for SOC under Power Constraints"@en .