. . . "RIV/00216305:26230/05:PU56455!RIV10-MSM-26230___" . "Smr\u010Dka, Ale\u0161" . "[427F43B23673]" . "The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too." . . . "High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design" . . . . "Springer-Verlag" . "P(GA102/04/0780), P(GA102/05/0723), Z(MSM6383917201)" . . "Berlin" . "978-3-540-29105-3" . . . . "High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design"@en . . . "Correct Hardware Design and Verification Methods" . "Saarbruecken" . "26230" . "High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design" . . "Vojnar, Tom\u00E1\u0161" . . "5"^^ . "3"^^ . . "2005-10-03+02:00"^^ . . "Matou\u0161ek, Petr" . "523308" . "formal analysis and verification, timed automata, parametric analysis, FPGA, hardware, computer networks
"@en . . "High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design"@en . "3"^^ . . "RIV/00216305:26230/05:PU56455" . . . "The paper presents high-level modelling and formal analysis and verification on an FPGA-based multigigabit network monitoring system called Scampi. Uppaal was applied in this work to establish some correctness and throughput results on a model intentionally built using patterns reusable in other similar projects. Some initial experiments with parametric analysis using TReX were performed too."@en . . .