. . . "Increasing network bandwidth enables creation of more efficient and new
client-server type applications but requires more computational power in the servers. This paper presents a qualitatively new approach to implementation of~the applications in such servers. The proposed  approach relies on the FPGA-based hardware accelerator board that supports implementation of the~computational core of the applications or pre/post-processing of the data in the FPGA. Usage of such board relieves the serveer from the network-related data processing while leaving more computational power to the application itself. This paper demonstrates the proposed approach and describes the developed application platform containing 1 or 10 Gbps network interface, PCI
interface, and CAM/SRAM/DRAM memory chips." . "3"^^ . . "Mart\u00EDnek, Tom\u00E1\u0161" . "FPGA-Based Platform for Network Applications"@cs . . "3"^^ . "FPGA-Based Platform for Network Applications"@en . . "Ko\u0159enek, Jan" . "[E1FBF41F575B]" . "FPGA-Based Platform for Network Applications" . . . "FPGA, network application, gmii, xgmii, PCI, bus master"@en . . "2005-04-13+02:00"^^ . "Proc. of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop" . . . "963-9364-48-7" . "University of West Hungary" . "FPGA-Based Platform for Network Applications"@cs . "FPGA-Based Platform for Network Applications"@en . . . "4"^^ . . "\u010Cl\u00E1nek se zab\u00EDv\u00E1 popisem vytvo\u0159en\u00E9 platformy pro s\u00ED\u0165ov\u00E9 aplikace.
"@cs . "Sopron" . "Z(MSM6383917201)" . . "Sopron" . . . . "RIV/00216305:26230/05:PU55726!RIV06-MSM-26230___" . "26230" . . "RIV/00216305:26230/05:PU55726" . "194-197" . "Zem\u010D\u00EDk, Pavel" . . "522034" . "FPGA-Based Platform for Network Applications" . "Increasing network bandwidth enables creation of more efficient and new
client-server type applications but requires more computational power in the servers. This paper presents a qualitatively new approach to implementation of~the applications in such servers. The proposed  approach relies on the FPGA-based hardware accelerator board that supports implementation of the~computational core of the applications or pre/post-processing of the data in the FPGA. Usage of such board relieves the serveer from the network-related data processing while leaving more computational power to the application itself. This paper demonstrates the proposed approach and describes the developed application platform containing 1 or 10 Gbps network interface, PCI
interface, and CAM/SRAM/DRAM memory chips."@en . .