"2003" . . . "8"^^ . "RIV/00216305:26230/03:PU42670" . "3"^^ . . "26230" . "0"^^ . "ElectronicsLetters.com - http://www.electronicsletters.com" . "[8F0E676FAAC5]" . "0"^^ . . . . "1213-161X" . "3"^^ . . "Current hardware graphics rendering engines efficiently process huge amount of triangle data, but are not as suitable when operating on point-based scenes. This paper presents an architectural design for point-based rendering. We are using a previously developed hardware model featuring FPGA, DSP and CAM memory." . "RIV/00216305:26230/03:PU42670!RIV/2004/GA0/262304/N" . . . . "Cache-Based Parallel Particle Rendering Engine" . . "CZ - \u010Cesk\u00E1 republika" . "0-7" . "P(GA102/02/0507)" . . . . "Herout, Adam" . "600248" . "particle, surfel, particle renderer, particle rendering engine, Field Programmable Gate Array - FPGA, Content Addressable Memory - CAM, Digital Signal Processor - DSP, Programmable Switching Matrix - PSM, Configurable Logic Block - CLB, cache, spatial da"@en . . . "Cache-Based Parallel Particle Rendering Engine"@en . . . "Cache-Based Parallel Particle Rendering Engine"@en . "Zem\u010D\u00EDk, Pavel" . "1" . . . . . "Ti\u0161novsk\u00FD, Pavel" . "Current hardware graphics rendering engines efficiently process huge amount of triangle data, but are not as suitable when operating on point-based scenes. This paper presents an architectural design for point-based rendering. We are using a previously developed hardware model featuring FPGA, DSP and CAM memory."@en . "Cache-Based Parallel Particle Rendering Engine" . . . .