"Kompresor a dekompresor hlavi\u010Dek pro 1 Gbps Ethernet slou\u017E\u00ED k hardwarov\u00E9 implementaci komprese TCP/IP a UDP/IP hlavi\u010Dek Ethernetov\u00E9ho toku. Navr\u017Een\u00E1 komprese pracuje na \u00FArovni linkov\u00E9 vrstvy. Modul kompresoru a dekompresoru je realizov\u00E1n tak, aby doch\u00E1zelo k co nejmen\u0161\u00ED latenci p\u0159en\u00E1\u0161en\u00FDch dat. Implementace byla testov\u00E1na na FPGA obvodu Altera Cyclone III (EP3C40F484C7)." . . . . . . . "26220" . . . "Kompresor a dekompresor hlavi\u010Dek pro 1 Gbps Ethernet, implementace pro FPGA"@cs . "HW kompresor hlavi\u010Dek" . "Kompresor a dekompresor hlavi\u010Dek pro 1 Gbps Ethernet, implementace pro FPGA" . "The header compressor and decompressor is designed for the hardware compression of 1 Gbps Ethernet headers like TCP/IP and UDP/IP. An implemented compression and decompression modules were designed with respect to the minimal delay of processed data, they work at link layer. The implementation was realized and tested at FPGA device Altera Cyclone III (EP3C40F484C7)."@en . . . . "SW lze vyu\u017E\u00EDt na v\u0161ech typech Ethernetov\u00FDch r\u00E1diov\u00FDch modem\u016F, slou\u017E\u00ED k zv\u00FD\u0161en\u00ED efektivity, spolehlivosti a \u00FAspo\u0159e energie p\u0159i p\u0159enosu dat." . "RIV/00216305:26220/12:PR26174" . "Kompresor a dekompresor hlavi\u010Dek pro 1 Gbps Ethernet, implementace pro FPGA"@cs . . . "http://www.urel.feec.vutbr.cz/index.php?page=software" . . "145198" . "Kompresor a dekompresor hlavi\u010Dek pro 1 Gbps Ethernet slou\u017E\u00ED k hardwarov\u00E9 implementaci komprese TCP/IP a UDP/IP hlavi\u010Dek Ethernetov\u00E9ho toku. Navr\u017Een\u00E1 komprese pracuje na \u00FArovni linkov\u00E9 vrstvy. Modul kompresoru a dekompresoru je realizov\u00E1n tak, aby doch\u00E1zelo k co nejmen\u0161\u00ED latenci p\u0159en\u00E1\u0161en\u00FDch dat. Implementace byla testov\u00E1na na FPGA obvodu Altera Cyclone III (EP3C40F484C7)."@cs . "\u0160tohanzl, Milan" . . "RIV/00216305:26220/12:PR26174!RIV13-MSM-26220___" . "Milan \u0160tohanzl \u00DAstav radioelektroniky Purky\u0148ova 118 612 00 Brno stohanzl@phd.feec.vutbr.cz" . . "Kompresor a dekompresor hlavi\u010Dek pro 1 Gbps Ethernet, implementace pro FPGA" . "Fedra, Zbyn\u011Bk" . . . . "1 Gbps Ethernet header compressor and decompressor, FPGA implementation"@en . "[B8EE38E18105]" . . . "1 Gbps Ethernet header compressor and decompressor, FPGA implementation"@en . . "2"^^ . . "FPGA, compression, header, dictionary"@en . "P(ED2.1.00/03.0072), P(EE2.3.20.0007), P(LD11081), S" . "2"^^ .