. "34th International Conference on Telecommunications and Signal Processing, TSP 2011" . "Budapest" . "238326" . . . "In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables." . "Neuveden" . "P(EE2.3.20.0007), P(GPP102/10/P513), S, Z(MSM0021630513)" . "RIV/00216305:26220/11:PU94781" . "2"^^ . "VHDL Procedure for Combinational Divider"@en . "RIV/00216305:26220/11:PU94781!RIV13-MSM-26220___" . . "[EED537D3556B]" . "divider, FPGA, implementation, procedure, static timing analysis, VHDL"@en . . . . . "VHDL Procedure for Combinational Divider"@en . . "Kolouch, Jarom\u00EDr" . "VHDL Procedure for Combinational Divider" . . "2"^^ . . "VHDL Procedure for Combinational Divider" . . . "In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices - amount of FPGA resources used and maximum delay, are given in tables."@en . . . . . . "Fedra, Zbyn\u011Bk" . . . . "Neuveden" . "978-1-4577-1761-1" . . "26220" . . . "3"^^ . . "2011-08-18+02:00"^^ .