"IP core pro generov\u00E1n\u00ED laditeln\u00FDch budic\u00EDch syntetizovateln\u00FDch sign\u00E1l\u016F"@cs . . "P(GA102/09/1628), Z(MSM0021630503)" . . "26220" . "[936B8F92CF82]" . . "IP core pro generov\u00E1n\u00ED laditeln\u00FDch budic\u00EDch syntetizovateln\u00FDch sign\u00E1l\u016F" . . "SINcore" . . . . "Bohrn, Marek" . . . "IP core pro generov\u00E1n\u00ED laditeln\u00FDch budic\u00EDch syntetizovateln\u00FDch sign\u00E1l\u016F"@cs . "Fujcik, Luk\u00E1\u0161" . "sensors, programmable circuits"@en . "2"^^ . . "RIV/00216305:26220/10:PR24922" . "nen\u00ED T10/5.27" . "2"^^ . . "IP core pro generov\u00E1n\u00ED laditeln\u00FDch budic\u00EDch syntetizovateln\u00FDch sign\u00E1l\u016F" . . "IP core for generation of synthesized tunable reference signals"@en . . "J\u00E1dro gener\u00E1toru harmonick\u00E9ho a troj\u00FAhelnikov\u00E9ho sign\u00E1lu je ur\u010Deno pro m\u011B\u0159\u00EDc\u00ED a testovac\u00ED \u00FA\u010Dely zejm\u00E9na v senzorick\u00FDch aplikac\u00EDch. Jedn\u00E1 se o funk\u010Dn\u00ED model v jazyce VHDL. V\u00FDhodou je vysok\u00E1 p\u0159enositelnost a kompatibilita mezi v\u0161emi obvody FPGA. J\u00E1dro je mo\u017En\u00E9 implementovat tak\u00E9 na \u010Dip."@cs . . "J\u00E1dro gener\u00E1toru harmonick\u00E9ho a troj\u00FAhelnikov\u00E9ho sign\u00E1lu je ur\u010Deno pro m\u011B\u0159\u00EDc\u00ED a testovac\u00ED \u00FA\u010Dely zejm\u00E9na v senzorick\u00FDch aplikac\u00EDch. Jedn\u00E1 se o funk\u010Dn\u00ED model v jazyce VHDL. V\u00FDhodou je vysok\u00E1 p\u0159enositelnost a kompatibilita mezi v\u0161emi obvody FPGA. J\u00E1dro je mo\u017En\u00E9 implementovat tak\u00E9 na \u010Dip." . . . "Bohrn, Marek" . "J\u00E1dro je pops\u00E1no v jazyce VHDL. Pracovn\u00ED frekvence j\u00E1dra je 10MHz. V\u00FDstupn\u00ED frekvence harmonick\u00E9ho a troj\u00FAheln\u00EDkov\u00E9ho sign\u00E1lu je nastaviteln\u00E1 a p\u0159eladiteln\u00E1 v rozsahu 1Hz a\u017E 100kHz. Rozli\u0161en\u00ED v\u00FDstupn\u00EDho sign\u00E1lu je od 12 do 42 bit." . "264911" . . "RIV/00216305:26220/10:PR24922!RIV11-GA0-26220___" . . "IP core for generation of synthesized tunable reference signals"@en . "Harmonic and triangle Generator IP core is designed for measurements and testing of circuits. Core is described in VHDL language. Main advantage is portability and compactibility on all FPGA chips. The core can be also implemented on chip."@en .