"1"^^ . "Brno, \u010CR" . "Proceedings of the 15th Conference Student EEICT 2009" . "Serial Communication Peripheries Development in FPGA"@cs . . "1"^^ . "Serial Communication Peripheries Development in FPGA"@cs . "340880" . "This project is about periphery, which from parallel input signals make one output serial signal. This serial signal contains start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. After parity bit there is one stop bit or there are two stop bits. The periphery is programmed in VHDL language and implemented in FPGA device. After simulation the implementation was realized in Xilinx ISE WebPACK and tested in real time."@cs . "This project is about periphery, which from parallel input signals make one output serial signal. This serial signal contains start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. After parity bit there is one stop bit or there are two stop bits. The periphery is programmed in VHDL language and implemented in FPGA device. After simulation the implementation was realized in Xilinx ISE WebPACK and tested in real time." . "3"^^ . . . "Serial Communication Peripheries Development in FPGA"@en . "RIV/00216305:26220/09:PU80924!RIV10-MSM-26220___" . . . "S" . "[7D178BA35AD6]" . . . . "Serial Communication Peripheries Development in FPGA" . "\u0160traus, Pavel" . "Serial Communication Peripheries Development in FPGA" . . "978-80-214-3867-5" . "2009-04-23+02:00"^^ . "26220" . . "Serial Communication Peripheries Development in FPGA"@en . . . "VHDL, UART, Virtex-II"@en . "FEKT VUT v Brn\u011B" . . . "Vysok\u00E9 u\u010Den\u00ED technick\u00E9 v Brn\u011B" . "This project is about periphery, which from parallel input signals make one output serial signal. This serial signal contains start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count is set with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. After parity bit there is one stop bit or there are two stop bits. The periphery is programmed in VHDL language and implemented in FPGA device. After simulation the implementation was realized in Xilinx ISE WebPACK and tested in real time."@en . "RIV/00216305:26220/09:PU80924" . .