"phase locked-loop"@en . "978-80-214-3534-6" . "N\u00E1vrh a v\u00FDvoj f\u00E1zov\u00E9ho z\u00E1v\u011Bsu"@cs . . . "Vrba, Radim\u00EDr" . "RIV/00216305:26220/07:PU71518!RIV08-GA0-26220___" . . . . . "\u010Cl\u00E1nek popisuje n\u00E1vrh a v\u00FDvoj f\u00E1zov\u00E9ho z\u00E1v\u011Bsu, kter\u00FD je ur\u010Den pro synchronizaci s modul\u00E1torem sigma-delta."@cs . "Design of Integer Phase Locked Loop"@en . "MIKROSYN. Nov\u00E9 trendy v mikroelektronick\u00FDch syst\u00E9mech a nanotechnologi\u00EDch.. Semin\u00E1\u0159 o v\u00FDsledc\u00EDch v\u00FDzkumn\u00E9ho z\u00E1m\u011Bru MSM 0021630503 v roce 2007. Sborn\u00EDk p\u0159\u00EDsp\u011Bvk\u016F" . "4"^^ . "BRNO" . "Brno" . . . "P(GA102/05/0869), Z(MSM0021630503)" . . "4"^^ . . . . . . "H\u00E1ze, Ji\u0159\u00ED" . . "The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process ."@en . "Prokop, Roman" . . "N\u00E1vrh a v\u00FDvoj f\u00E1zov\u00E9ho z\u00E1v\u011Bsu"@cs . "7"^^ . "416424" . "Design of Integer Phase Locked Loop" . . . "Ing. Zden\u011Bk Novotn\u00FD CSc." . "The paper describes the design procedure of phase locked loop (PLL). This PLL is used in band-pass sigma-delta modulator to synchronise the input slow sine-wave signal with driving clock of modulator. It generates 62,5 kHz rectangle driving signal. The paper also shows simulation results, which confirm the design process ." . . "RIV/00216305:26220/07:PU71518" . "27-33" . "2007-09-20+02:00"^^ . "Design of Integer Phase Locked Loop" . "[DD88D710327F]" . "Design of Integer Phase Locked Loop"@en . "Fujcik, Luk\u00E1\u0161" . "26220" .