. "P(GA102/05/0571), P(GA102/05/0732), Z(MSM0021630513)" . "211-214" . . "Data Recovery, FPGA, VHDL-AMS, simulation, CDR."@en . . "978-80-214-3390-8" . "Brno" . . . "1"^^ . . . . "Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals" . "26220" . "Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals"@en . . "Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals"@en . . . "Department of Radio Electronics, Brno University" . "Kub\u00ED\u010Dek, Michal" . . "Simulace obnovy datov\u00E9ho a hodinov\u00E9ho sign\u00E1lu ze siln\u011B zaru\u0161en\u00FDch sign\u00E1l\u016F"@cs . . "449998" . "Simulaton of Digital Clock and Data Recovery of Strongly Disturbed Signals" . "The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic\u2019s SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design."@en . . "RIV/00216305:26220/07:PU67574!RIV07-GA0-26220___" . . . "RIV/00216305:26220/07:PU67574" . . . "The paper describes a simulation model of a software and hardware recovery circuit. Performance of both models is compared and drawbacks of software recovery are discussed. To model different link conditions, signal source and data path models were created (to model jitter and noise of received signal). All simulations were performed in the Mentor Graphic\u2019s SystemVision 4.4 environment using VHDL-AMS models of signal source, data path and recovery circuits. The software recovery algorithm is written in synthesizable subset of VHDL and can be directly used as a part of an FPGA design." . . "MJ servicsBo\u017Eet\u011Bchova 133, 612 00 Brno, Czech Republic" . "2007-04-24+02:00"^^ . "Simulace obnovy datov\u00E9ho a hodinov\u00E9ho sign\u00E1lu ze siln\u011B zaru\u0161en\u00FDch sign\u00E1l\u016F"@cs . "4"^^ . "Proceedings of 17th International Conference Radioelektronika 2007" . "\u010Cl\u00E1nek se zab\u00FDv\u00E1 simulac\u00ED model\u016F softwarov\u00E9 a hardwarov\u00E9 obnovy hodinov\u00E9ho sign\u00E1lu. Jsou porovn\u00E1ny vlastnosti obou metod a shrnuty jejich v\u00FDhody a nev\u00FDhody. Aby bylo mo\u017En\u00E9 modelovat r\u016Fzn\u00E9 podm\u00EDnky na p\u0159enosov\u00E9 trase, byl vytvo\u0159en model zdroje datov\u00E9ho sign\u00E1lu a digit\u00E1ln\u00EDho kan\u00E1lu (lze modelovat jitter i \u0161um p\u0159ij\u00EDman\u00E9ho sign\u00E1lu). V\u0161echny simulace byly provedeny v prost\u0159ed\u00ED SystemVision 4.4 firmy Mentor Graphics pomoc\u00ED model\u016F popsan\u00FDch jazykem VHDL-AMS (zdroj sign\u00E1lu, p\u0159enosov\u00FD kan\u00E1l a hardwarov\u00E1 obnova dat). Model softwarov\u00E9 obnovy dat byl pops\u00E1n pomoc\u00ED syntetizovateln\u00E9 \u010D\u00E1sti jazyka VHDL a m\u016F\u017Ee tak b\u00FDt p\u0159\u00EDmo pou\u017Eit jako sou\u010D\u00E1st designu pro FPGA."@cs . . "1"^^ . "[2B8CB3C28C42]" . .