"486184" . . "4"^^ . . . . "Vrba, Radim\u00EDr" . "6"^^ . "4"^^ . "Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration" . "Modelov\u00E1n\u00ED 10-bitov\u00E9ho, 40 MHz, n\u00EDzkop\u0159\u00EDkonov\u00E9ho \u0159et\u011Bzov\u00E9ho p\u0159evodn\u00EDku AD, kter\u00FD vyu\u017E\u00EDv\u00E1 novou kalibra\u010Dn\u00ED metodu"@cs . . "The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operationalamplifier (op-amp) sharing technique \u2013 shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock feedthrough from digital part through the switches, capacitor mismatch etc.) are avoided using the fully differential circuitry in conjunction with novel background calibration. The special OTAs and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the OTAs was taken into account too. The finite OTA dc gain problem is solved in digitaldomain using background calibration. The capacitor mismatch and OTA offset are compensated in the same manner as me" . "Morne" . . . . . "Sajdl, Ond\u0159ej" . . "Proceedings of ICN 2006, ICONS 2006, MCL 2006" . . "Pipelined ADC, switched-capacitors, background calibration, portable devices"@en . "The article presents new background calibration technique, which is utilized in new 10-bit low power switched-capacitor(SC) pipelined ADC. Since portable applications demand for low power consumption, it is one of the most important issues considered in the design. A modified operationalamplifier (op-amp) sharing technique \u2013 shared operational transconductance amplifier (OTA) was used to decrease the power usage as well as capacitor scaling approach. The problems caused by SC (i.e. clock feedthrough from digital part through the switches, capacitor mismatch etc.) are avoided using the fully differential circuitry in conjunction with novel background calibration. The special OTAs and comparators were designed for this purpose and to obtain large bandwidth. The power consumption of the OTAs was taken into account too. The finite OTA dc gain problem is solved in digitaldomain using background calibration. The capacitor mismatch and OTA offset are compensated in the same manner as me"@en . "Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration"@en . "Mauritius" . "Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration"@en . . "26220" . "RIV/00216305:26220/06:PU57508!RIV07-GA0-26220___" . . . "IEEE" . "\u010Cl\u00E1nek popisuje novou kalibra\u010Dn\u00ED techniku, kter\u00E1 je pou\u017Eita v 10-bitov\u00E9m \u0159et\u011Bzov\u00E9m p\u0159evodn\u00EDku DA. P\u0159evodn\u00EDk pracuje v technice sp\u00EDnan\u00FDch kapacitor\u016F. Proto\u017Ee je p\u0159evodn\u00EDk ur\u010Den pro aplikace s bateriov\u00FDm nap\u00E1jen\u00EDm, byla uva\u017Eov\u00E1na i pot\u0159eba co nejmen\u0161\u00ED spot\u0159eby obvodu. Spolu s novou kalibra\u010Dn\u00ED technikou byly pou\u017Eity modifikovan\u00E9 obvodov\u00E9 techniky, kter\u00E9 dohromady \u0159e\u0161\u00ED probl\u00E9my spojen\u00E9 s technikou SC."@cs . "Modeling of 10-bits, 40 MHz, low power pipelined ADC utilizing novel background calibration" . . . . "116-121" . . . . "2006-04-26+02:00"^^ . "[8CC7786B1007]" . "RIV/00216305:26220/06:PU57508" . "H\u00E1ze, Ji\u0159\u00ED" . "Modelov\u00E1n\u00ED 10-bitov\u00E9ho, 40 MHz, n\u00EDzkop\u0159\u00EDkonov\u00E9ho \u0159et\u011Bzov\u00E9ho p\u0159evodn\u00EDku AD, kter\u00FD vyu\u017E\u00EDv\u00E1 novou kalibra\u010Dn\u00ED metodu"@cs . . "P(FT-TA/050), P(GA102/05/0869), Z(MSM0021630503)" . . "0-7695-2552-0" . "Fujcik, Luk\u00E1\u0161" . .