"Mougel, Thibault" . . . . "P(GA102/05/0869), P(GD102/03/H105), Z(MSM0021630503)" . . "6"^^ . "[5693BA735903]" . "N\u00E1vrh decima\u010Dn\u00EDho filtru pro novou architekturu modul\u00E1toru sigma-delta"@cs . "THE FOURTEENT INTERNATIONAL SCIENTIFIC AND APPLIED SCIENCE CONFERENCE - ELECTRONICS ET'2005" . "517385" . "954-438-521-5" . . . "2"^^ . "Technical University of Sofia" . "58-63" . "2"^^ . "Design of decimation filter for novel Sigma-Delta modulator"@en . . . . "Sozopol" . . "26220" . . "RIV/00216305:26220/05:PU53780!RIV07-GA0-26220___" . "Design of decimation filter for novel Sigma-Delta modulator" . "sigma-delta modulator, decimation filter"@en . . . . "Tento \u010Dl\u00E1nek popisuje kroky, kter\u00E9 jsou nutn\u00E9 pou\u017E\u00EDt pro n\u00E1vrh decima\u010Dn\u00EDho filtru. Parametry decima\u010Dn\u00EDho filtru jsou odvozeny ze specifikace modul\u00E1toru sigma-delta. K n\u00E1vrhu decima\u010Dn\u00EDho filtru byly pou\u017Eity programy Matlab a MathCAD. Byly navr\u017Eeny dv\u011B verze decima\u010Dn\u00EDho filtru. Prvn\u00ED verze decima\u010Dn\u00EDho je ur\u010Dena pro programovateln\u00E9 logick\u00E9 obvody a druh\u00E1 verze je ur\u010Dena pro n\u00E1vrh na \u010Dip v technologii AMIS CMOS 0.7 \u00B5m."@cs . "This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 \u00B5m technology." . "N\u00E1vrh decima\u010Dn\u00EDho filtru pro novou architekturu modul\u00E1toru sigma-delta"@cs . . . "Design of decimation filter for novel Sigma-Delta modulator"@en . "Design of decimation filter for novel Sigma-Delta modulator" . "Mougel, Thibault" . "Bulgaria" . . . "RIV/00216305:26220/05:PU53780" . "2005-09-21+02:00"^^ . "Fujcik, Luk\u00E1\u0161" . "This paper describes steps involved in a new VHDL design of a decimation filter for a sigma-delta (Σ∆) modulator. Parameters of decimation filter are derived from the specifications of the overall Σ∆ modulator. Using Matlab and MathCAD tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The first version is programmed and tested on a FPGA chip. Then second version was created for Cadence software tool to implement into a chip in the AMIS CMOS 0.7 \u00B5m technology."@en .