"Vrba, Radim\u00EDr" . "Mougel, Thibault" . "RIV/00216305:26220/05:PU51427!RIV07-GA0-26220___" . "3"^^ . . "\u010Cl\u00E1nek popisuje novou architekturu p\u0159evodn\u00EDku sigma-delta vy\u0161\u0161\u00EDho \u0159\u00E1du pro senzorov\u00E9 m\u011B\u0159en\u00ED. P\u0159evodn\u00EDk s dvoustup\u0148ov\u00FDm kvantovac\u00EDm procesem je vyu\u017Eit jako v\u00EDcebitov\u00FD kvantovac\u00ED obvod.Prezentov\u00E1na acrhitektura byla namodelov\u00E1na v prost\u0159ed\u00ED Matlab Simulink.V \u010Dl\u00E1nku je tak\u00E9 prezentov\u00E1n n\u00E1vrh decima\u010Dn\u00EDho filtru pro danou architekturu modul\u00E1toru sigma-delta."@cs . . . . "Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement"@en . . . "80-214-2990-9" . "This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages)." . . . "P(GA102/05/0869), P(GD102/03/H105), Z(MSM0021630503)" . . "This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages)."@en . . "RIV/00216305:26220/05:PU51427" . "26220" . "Ing. Zden\u011Bk Novotn\u00FD CSc." . "148-153" . "Modelov\u00E1n\u00ED a n\u00E1vrh nov\u00E9 architektury modul\u00E1toru sigma-delta pro senzorov\u00E9 m\u011B\u0159en\u00ED."@cs . "EDS'05 IMAPS CS INTERNATIONAL CONFERENCE PROCEEDINGS" . "Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement"@en . "Brno" . "Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement" . "2005-09-15+02:00"^^ . "Brno" . . "[EE28D9A744A6]" . . . . "Modeling and Design of a Novel Architecture of Sigma-Delta Converter for Sensor Measurement" . . "Mougel, Thibault" . . . . "Modelov\u00E1n\u00ED a n\u00E1vrh nov\u00E9 architektury modul\u00E1toru sigma-delta pro senzorov\u00E9 m\u011B\u0159en\u00ED."@cs . . "Fujcik, Luk\u00E1\u0161" . "sigma-delta modulation, decimation filter, modeling"@en . "530555" . "6"^^ . . "3"^^ .