"Switched-current RSD analog-to-digital converter" . "Crete, Greece" . . . "RSD algorithm was implemented to cycles or pipelined switched-current analog-to-digital converter (ADC), where resolution of sub converter is 1,5 bit. This implementation is well known. Implementation of RSD algorithm to ADC with 2,5-bit sub converter is presented in this paper. The most critical blocs in classical ADC are reference currents sources and comparators. Usage of this algorithm decrease inaccuracy of these blocks impact on accuracy of full ADC. Same current sources can by designed using classicall current mirors and same current sources must by designed using switched current second generation memory cells." . "Switched-current RSD analog-to-digital converter"@en . "4"^^ . "RIV/00216305:26220/04:PU46468" . . "RSD algoritmus je implementov\u00E1n do cyklick\u00E9ho nebo algoritmick\u00E9ho p\u0159evodn\u00EDku AD se sp\u00EDnan\u00FDmi proudy. Tato implementace je zn\u00E1ma. Tato implementace, kde d\u00EDl\u010D\u00ED p\u0159evodn\u00EDk je 2,5-bitov\u00FD je nov\u00E1."@cs . "80-214-2819-8" . . "4"^^ . . "67-70" . . "A/D converters, Reference signals, Current amplifiers, Switched current technique, RSD algorithm, Semiflash A/D converters"@en . "Fujcik, Luk\u00E1\u0161" . "Switched-current RSD analog-to-digital converter" . "[1CA4D97CFEE4]" . . . "Sko\u010Ddopole, Michal" . "AD p\u0159evodn\u00EDk RSD se sp\u00EDnan\u00FDmi proudy"@cs . . . "Socrates Workshop 2004. Intensive Training Programme in Electronic System Design. Proceedings." . . . . . "4"^^ . "P(GA102/03/0619), P(GD102/03/H105)" . "2004-09-14+02:00"^^ . "RIV/00216305:26220/04:PU46468!RIV/2005/GA0/262205/N" . "Vrba, Radim\u00EDr" . . . . . . "26220" . . "Technological Institute of Crete, Greece" . "AD p\u0159evodn\u00EDk RSD se sp\u00EDnan\u00FDmi proudy"@cs . "589200" . "H\u00E1ze, Ji\u0159\u00ED" . "Switched-current RSD analog-to-digital converter"@en . . . "RSD algorithm was implemented to cycles or pipelined switched-current analog-to-digital converter (ADC), where resolution of sub converter is 1,5 bit. This implementation is well known. Implementation of RSD algorithm to ADC with 2,5-bit sub converter is presented in this paper. The most critical blocs in classical ADC are reference currents sources and comparators. Usage of this algorithm decrease inaccuracy of these blocks impact on accuracy of full ADC. Same current sources can by designed using classicall current mirors and same current sources must by designed using switched current second generation memory cells."@en . "Technological Institute of Crete, Chania, Greece" . .