"P(GA102/02/1312), Z(MSM 262200022)" . "Reduction of the transistor mismaches effects in SI circuits"@en . "Technological Institute of Crete, Chania, Greece" . . . . . "switched current circuit, transistor mismatching"@en . "Reduction of the transistor mismaches effects in SI circuits" . "Reduction of the transistor mismaches effects in SI circuits"@en . . . "Proceedings of the Socrates Workshop 2004" . "RIV/00216305:26220/04:PU46404!RIV06-GA0-26220___" . "80-214-2819-8" . "5"^^ . "Redukce vlivu rozd\u00EDln\u00FDch vlastnost\u00ED tranzistor\u016F na obvody se sp\u00EDnan\u00FDmi proudy"@cs . "2004-09-14+02:00"^^ . . "Technological Institute of Chania" . "Chania" . "3"^^ . . . . . "Jsou uvedeny obvody se sp\u00EDnan\u00FDmi proudy (SI) se zmen\u0161en\u00FDm vlivem shodnosti tranzistor\u016F. Zmen\u0161en\u00ED tohoto vlivu je doc\u00EDleno modifikac\u00ED ji\u017E zn\u00E1m\u00E9 SI z\u00E1kladn\u00ED bu\u0148ky tak, \u017Ee je omezen po\u010Det pot\u0159ebn\u00FDch proudov\u00FDch zrcadel. Tyto bu\u0148ky budou pou\u017Eity jako stavebn\u00EDbloky pro komplexn\u00ED obvody zpracov\u00E1n\u00ED vzorkovan\u00E9ho sign\u00E1lu. Jako p\u0159\u00EDklad byl navr\u017Een biline\u00E1rn\u00ED integr\u00E1tor se sp\u00EDnan\u00FDmi proudy."@cs . "Reduction of the transistor mismaches effects in SI circuits" . "3"^^ . . . "145-149" . "Musil, Vladislav" . . "RIV/00216305:26220/04:PU46404" . "Prokop, Roman" . . "[90283CEAFA8E]" . "Stehl\u00EDk, Ji\u0159\u00ED" . . "26220" . . "Redukce vlivu rozd\u00EDln\u00FDch vlastnost\u00ED tranzistor\u016F na obvody se sp\u00EDnan\u00FDmi proudy"@cs . "The switched current (SI) circuits with reduced effect of transistor mismatches are introduced. Elimination of this phenomenon is achieved by a modification of an already known SI basic unit-delay cell, in such a way that the number of required current mirror circuits is reduced. These cells can be used as a building block of any arbitrary sampled-data transfer function. As an example, a SI bilinear integrator circuit was designed."@en . . "583922" . "The switched current (SI) circuits with reduced effect of transistor mismatches are introduced. Elimination of this phenomenon is achieved by a modification of an already known SI basic unit-delay cell, in such a way that the number of required current mirror circuits is reduced. These cells can be used as a building block of any arbitrary sampled-data transfer function. As an example, a SI bilinear integrator circuit was designed." . .