"V\u00FDvojov\u00FD kit s FPGA Altera"@cs . "[91CB0118B698]" . "The Altera development kit"@en . . "V\u00FDvojov\u00FD kit s FPGA Altera" . "VK" . "Beran, Ladislav" . "RIV/00216275:25530/14:39898474!RIV15-MSM-25530___" . "1"^^ . "V\u00FDvojov\u00FD kit s FPGA Altera je postaven na hradlov\u00E9m poli \u0159ady Cyclone II, typ EP2C35F672C8. V\u00FDvojov\u00FD kit je nap\u00E1jen stabilizovan\u00FDm stejnosm\u011Brn\u00FDm nap\u011Bt\u00EDm v rozsahu 7-15V. Proudov\u00E9 zat\u00ED\u017Een\u00ED nap\u00E1jen\u00EDcho zdroje minim\u00E1ln\u011B 1A. J\u00E1dro a perif\u00E9rie v\u00FDvojov\u00E9ho kitu je nap\u00E1jeno pomoc\u00ED dvou DC-DC m\u011Bni\u010D\u016F pro nap\u00E1jen\u00ED perif\u00E9ri\u00ED (+5 V a +3.3 V) a jednoho line\u00E1rn\u00EDho stabiliz\u00E1toru pro nap\u011Bt\u00ED j\u00E1dra FPGA (+1.2 V). Hradlov\u00E9 pole je mo\u017En\u00E9 programovat pomoc\u00ED JTAG program\u00E1toru nebo program\u00E1toru EPCS pam\u011Bti. Jako funk\u010Dn\u00ED vstupy/v\u00FDstupy m\u00E1 v\u00FDvojov\u00FD kit k dispozici celkem 4x8 datov\u00FDch v\u00FDvod\u016F + 8xzem. Vstup\u016F od u\u017Eivatele m\u00E1 v\u00FDvojov\u00FD kit celkem osm - \u010Dty\u0159i vstupy jako p\u0159ep\u00EDna\u010De a \u010Dty\u0159i vstupy jako tla\u010D\u00EDtka. Pro plnohodnotn\u00E9 zobrazen\u00ED v\u00FDstupn\u00ED informace z FPGA je k dispozici LCD displej 2x16 znak\u016F. Alternativou k zobrazen\u00ED v\u00FDstupn\u00ED informace m\u016F\u017Ee b\u00FDt sada \u010Dty\u0159 sedmisegmentov\u00FDch displej\u016F ovl\u00E1dan\u00FDch p\u0159es posuvn\u00FD registr CD4094. Pro p\u0159ipojen\u00ED k po\u010D\u00EDta\u010Dov\u00E9 s\u00EDti m\u00E1 v\u00FDvojov\u00FD kit p\u0159id\u00E1n ethernetov\u00FD p\u0159evodn\u00EDk. D\u00E1le je na DPS p\u0159id\u00E1na virtu\u00E1ln\u00ED seriov\u00E1 linka pro komunikaci s osobn\u00EDm po\u010D\u00EDta\u010Dem." . . "V\u00FDvojov\u00FD kit s FPGA Altera" . . "V\u00FDvojov\u00FD kit s FPGA Altera je postaven na hradlov\u00E9m poli \u0159ady Cyclone II, typ EP2C35F672C8. V\u00FDvojov\u00FD kit je nap\u00E1jen stabilizovan\u00FDm stejnosm\u011Brn\u00FDm nap\u011Bt\u00EDm v rozsahu 7-15V. Proudov\u00E9 zat\u00ED\u017Een\u00ED nap\u00E1jen\u00EDcho zdroje minim\u00E1ln\u011B 1A. J\u00E1dro a perif\u00E9rie v\u00FDvojov\u00E9ho kitu je nap\u00E1jeno pomoc\u00ED dvou DC-DC m\u011Bni\u010D\u016F pro nap\u00E1jen\u00ED perif\u00E9ri\u00ED (+5 V a +3.3 V) a jednoho line\u00E1rn\u00EDho stabiliz\u00E1toru pro nap\u011Bt\u00ED j\u00E1dra FPGA (+1.2 V). Hradlov\u00E9 pole je mo\u017En\u00E9 programovat pomoc\u00ED JTAG program\u00E1toru nebo program\u00E1toru EPCS pam\u011Bti. Jako funk\u010Dn\u00ED vstupy/v\u00FDstupy m\u00E1 v\u00FDvojov\u00FD kit k dispozici celkem 4x8 datov\u00FDch v\u00FDvod\u016F + 8xzem. Vstup\u016F od u\u017Eivatele m\u00E1 v\u00FDvojov\u00FD kit celkem osm - \u010Dty\u0159i vstupy jako p\u0159ep\u00EDna\u010De a \u010Dty\u0159i vstupy jako tla\u010D\u00EDtka. Pro plnohodnotn\u00E9 zobrazen\u00ED v\u00FDstupn\u00ED informace z FPGA je k dispozici LCD displej 2x16 znak\u016F. Alternativou k zobrazen\u00ED v\u00FDstupn\u00ED informace m\u016F\u017Ee b\u00FDt sada \u010Dty\u0159 sedmisegmentov\u00FDch displej\u016F ovl\u00E1dan\u00FDch p\u0159es posuvn\u00FD registr CD4094. Pro p\u0159ipojen\u00ED k po\u010D\u00EDta\u010Dov\u00E9 s\u00EDti m\u00E1 v\u00FDvojov\u00FD kit p\u0159id\u00E1n ethernetov\u00FD p\u0159evodn\u00EDk. D\u00E1le je na DPS p\u0159id\u00E1na virtu\u00E1ln\u00ED seriov\u00E1 linka pro komunikaci s osobn\u00EDm po\u010D\u00EDta\u010Dem."@cs . . "1"^^ . "The Altera development kit"@en . . "FPGA Altera - Cyclone II EP2C35F672C8, Etehernet, SDRAM, SRAM, 16x2 LCD displej, 4xsedmisegmentov\u00FD LCD displej" . "nejsou stanoveny" . . "V\u00FDvojov\u00FD kit s FPGA Altera"@cs . . . "55468" . "The development kit is based on Field Programming Gate Array Cyclone II series, type EP2C35F672C8. Development kit is powered from external source in range 7 to 15 V and minimal 1A of current. The core and peripheral is powered from two DC-DC switching power supplies. The first DC-DC power supply is used for peripheral (+3.3 V), second DC-DC power supply is used for core (+1.2 V). The FPGA can be programmed using two programming interfaces - JTAG interface and EPCS programmer interface. As functional outputs have development kit a totally 32 digital IO. Development kit has totally eight inputs- four switches and four buttons. To display text information development kit has two possibilities. First possibility is show text at LCD 16x2 character display. Second possibility is show text at seven-segment display. Development kit has also Ethernet and virtual serial link."@en . . "25530" . . . "Development kit, Altera"@en . . "S" . . "RIV/00216275:25530/14:39898474" . . . . .