. "0"^^ . . . . "1"^^ . "0"^^ . . "0"^^ . "N\u00E1vrhov\u00FD syst\u00E9m pro automatizaci n\u00E1vrhu komunika\u010Dn\u00EDch procesor\u016F na b\u00E1zi obvod\u016F FPGA" . "0"^^ . "http://www.isvav.cz/projectDetail.do?rowId=OK 173"^^ . "A CAD System for Automatic Design of FPGA-Based Communication ProcessorsP"@en . . "OK 173" . . . "C\u00EDlem v\u00FDzkumn\u00FDch a v\u00FDvojov\u00FDch prac\u00ED tohoto projektu je v\u00FDvoj programov\u00FDch prost\u0159edk\u016F, kter\u00E9 zrychl\u00ED a zkvalitn\u00ED n\u00E1vrh mikroelektronick\u00FDch syst\u00E9m\u016F a p\u0159isp\u011Bj\u00ED k \u0159\u00EDzen\u00ED kvality p\u0159\u00EDslu\u0161n\u00FDch v\u00FDrobk\u016F. Dos\u00E1hne se toho pou\u017Eit\u00EDm grafick\u00E9ho jazyka pro popis chov\u00E1n\u00ED syst\u00E9mu a proveden\u00EDm automatick\u00E9 synt\u00E9zy, tj. automatick\u00E9 transformace specifikace syst\u00E9mu do jeho implementace. Projekt se soust\u0159e\u010Fuje na specifickou t\u0159\u00EDdu aplikac\u00ED a na programovateln\u00E1 hradlov\u00E1 pole (FPGA) jako na z\u00E1klad implementace syst\u00E9mu." . . . . . .