. "1"^^ . "http://www.isvav.cz/projectDetail.do?rowId=GA102/04/2137"^^ . "2"^^ . . . . . . . "0"^^ . . "Neuvedeno."@en . "56"^^ . "The project concentrates on design of reconfigurable circuits implemented in the field-programmable gate array (FPGA) technology, with a special consideration of reaching high reliability of the designed functional unit. This will be achieved especially by creating an effective reconfiguration algorithm for FPGAs. The reconfiguration will make it possible to eliminate permanent errors that occur in individual function blocks and error recovery in case of transient errors. Two systems will be created - adiagnostic system will control and evaluate a periodic diagnostics and another system will implement an autonomous built-in self test inside each function block. We will apply methods we have been developing for built-in test pattern generation. We expect to decrease the amount of circuitry needed for diagnostics when compared to currently used solutions while maintaining its diagnostic coverage. For the integration of the above mentioned diagnostic methods we will use existing FPGA circuits that"@en . "Nejv\u00FDznamn\u011Bj\u0161\u00EDmi v\u00FDsledky projektu jsou: Realizace diagnostick\u00E9ho syst\u00E9mu SoC na obvod\u011B ATMEL FPSLIC. Tento syst\u00E9m byl detailn\u011B pops\u00E1n v\u00A0 p\u0159edlo\u017Een\u00E9\u00A0diserta\u010Dn\u00ED pr\u00E1ci Ing. Z. Madera a d\u00E1le \u00A0publikov\u00E1n na r\u016Fzn\u00FDch konferenc\u00EDch, p\u0159ipravuje se \u010Dasopiseck\u00E1 pub"@cs . . . "N\u00E1vrh vysoce spolehliv\u00FDch \u0159\u00EDd\u00EDc\u00EDch syst\u00E9m\u016F pomoc\u00ED dynamicky rekonfigurovateln\u00FDch obvod\u016F FPGA" . "Projekt je zam\u011B\u0159en na n\u00E1vrh rekonfigurovateln\u00FDch obvod\u016F na b\u00E1zi hradlov\u00FDch pol\u00ED s d\u016Frazem na dosa\u017Een\u00ED vysok\u00E9 spolehlivosti navr\u017Een\u00E9ho funk\u010Dn\u00EDho celku. Tohoto c\u00EDle chceme dos\u00E1hnout zejm\u00E9na vytvo\u0159en\u00EDm efektivn\u00EDho algoritmu rekonfigurace FPGA. Rekonfiguraceumo\u017En\u00ED eliminaci trval\u00FDch poruch vznikl\u00FDch v jednotliv\u00FDch funk\u010Dn\u00EDch bloc\u00EDch a zotaven\u00ED po poruch\u00E1ch do\u010Dasn\u00FDch. Bude vytvo\u0159en diagnostick\u00FD syst\u00E9m \u0159\u00EDzen\u00ED a vyhodnocen\u00ED periodick\u00E9 diagnostiky a syst\u00E9m autonomn\u00ED vestav\u011Bn\u00E9 diagnostiky uvnit\u0159 ka\u017Ed\u00E9ho funk\u010Dn\u00EDhobloku. Budeme aplikovat n\u00E1mi vyv\u00EDjen\u00E9 metody komprese testovac\u00EDch vzork\u016F pro vestav\u011Bnou diagnostiku. Nov\u00E1 metoda bude vyu\u017Eita ve vestav\u011Bn\u00FDch gener\u00E1torech testovacich vzork\u016F, o\u010Dek\u00E1v\u00E1me sn\u00ED\u017Een\u00ED mno\u017Estv\u00ED technick\u00E9ho vybaven\u00ED pro diagnostiku oproti st\u00E1vaj\u00EDc\u00EDm pou\u017E\u00EDvan\u00FDm \u0159e\u0161en\u00EDm p\u0159i zachov\u00E1n\u00ED m\u00EDry diagnostick\u00E9ho pokryt\u00ED. Pro integraci jednotliv\u00FDch v\u00FD\u0161e uveden\u00FDch diagnostick\u00FDch prost\u0159edk\u016F vyu\u017Eijeme n\u011Bkter\u00FD z obvod\u016F podporuj\u00EDc\u00EDch dynamickou rekonfiguraci, nap\u0159. Xilinx Virtex a Atmel AT40K, AT94K." . "56"^^ . "GA102/04/2137" . . "2007-10-16+02:00"^^ . . . . . . . "The most siginificant achievements of the project are:An implementation of a diagnostic SoC system in the Atmel FPSLIC device. This system has been\u00A0described in detail in the PhD thesis\u00A0written by\u00A0Ing. Z. Mader and further published at different conferen"@en . . . . "Design of highly reliable control systems built on dynamically reconfigurable FPGAs."@en .