. "0"^^ . "Formal approaches in digital circuit diagnostics - testable design verification"@en . . . . . . . . . . . "Form\u00E1ln\u00ED postupy v diagnostice \u010D\u00EDslicov\u00FDch obvod\u016F - verifikace testovateln\u00E9ho n\u00E1vrhu" . . . "Projekt p\u0159inesl nov\u00E9 poznatky v oblasti vytvo\u0159en\u00ED form\u00E1ln\u00EDch postup\u016F pro anal\u00FDzu testovatelnosti \u010D\u00EDslicov\u00FDch obvod\u016F. Z\u00E1v\u011Bre\u010Dn\u00E1 karta poskytuje adekv\u00E1tn\u00ED \u00FAdaje. Aplika\u010Dn\u00ED v\u00FDznam projektu spo\u010D\u00EDv\u00E1 v n\u00E1vazn\u00E9m n\u00E1vrhu snadno testovateln\u00FDch obvod\u016F; sou\u010D\u00E1st\u00ED pr"@cs . "Neuvedeno."@en . "http://www.isvav.cz/projectDetail.do?rowId=GA102/01/1531"^^ . "72"^^ . . "72"^^ . "1"^^ . "GA102/01/1531" . "2008-05-30+02:00"^^ . "Nar\u016Fstaj\u00EDc\u00ED slo\u017Eitost \u010D\u00EDslicov\u00FDch obvod\u016F klade stale vy\u0161\u0161\u00ED n\u00E1roky na jejich testov\u00E1n\u00ED. Uplatn\u011Bn\u00ED diagnostick\u00FDch princip\u016F se stalo ned\u00EDlnou sou\u010D\u00E1st\u00ED synt\u00E9zy \u010D\u00EDslicov\u00FDch obvod\u016F. Sou\u010Dasn\u011B s prob\u00EDhaj\u00EDc\u00ED synt\u00E9zou obvodu jsou tedy zva\u017Eov\u00E1ny mo\u017Enosti jeho testo" . "2"^^ . . "The growing complexity of integrated circuits confronts the manufacturers with the problem of testability. The implementation of diagnostic principles has become an integral part of the process of digital circuit synthesis. During the synthesis the topic"@en . .