"2008-12-31+01:00"^^ . "30"^^ . . "The project aims at creating a new technology for diagnosing SoC-type digital circuits; project outputs will be a prototype and methodology. The method used for testing SoC circuits will be based on the so-called RESPIN architecture (IEEE P1500 compliant). The RESPIN architecture considers reconfiguration of each circuit core so that each core can be tested by the cores in its neighbourhood. Test vectors can be applied in a compressed form and the decompression can be done in the circuit using the neighbouring reconfigurable cores. The compressed test vectors for this architecture will be generated using the COMPAS tool designed and implemented by the applicant's team. The prototype will be implemented using the FPGA circuits from Atmel. To improve the testability of the designed circuits a tool will be created that will speed up fault simulation using circuit models implemented in dynamically reconfigurable FPGA circuits."@en . . "30"^^ . "http://www.isvav.cz/projectDetail.do?rowId=1QS108040510"^^ . "Technologie pro zlep\u0161en\u00ED testovatelnosti modern\u00EDch \u010D\u00EDslicov\u00FDch obvod\u016F" . . "2008-02-21+01:00"^^ . "Projekt si klade za c\u00EDl vytvo\u0159it novou technologii, jej\u00ED\u017E v\u00FDsledkem bude prototyp a n\u00E1vod, jak prov\u00E1d\u011Bt diagnostiku SoC obvodu. Metoda, kterou chceme pou\u017E\u00EDt pro testov\u00E1n\u00ED SoC obvod\u016F je zalo\u017Eena na tzv. RESPIN architektu\u0159e, kompatibiln\u00ED s normou IEEE P1500. RESPIN architektura umo\u017E\u0148uje rekonfigurovat zapojen\u00ED jednotliv\u00FDch jader obvodu tak, \u017Ee ka\u017Ed\u00E9 j\u00E1dro je testov\u00E1no za pomoc\u00ED jader okoln\u00EDch. Testovac\u00ED data mohou b\u00FDt p\u0159en\u00E1\u0161ena v komprimovan\u00E9m tvaru a jejich dekomprese bude prov\u00E1d\u011Bna s pomoc\u00ED okoln\u00EDch rekonfigurovan\u00FDch jader a\u017E uvnit\u0159 obvodu. Pro tuto architekturu budou generov\u00E1ny komprimovan\u00E9 testovac\u00ED posloupnosti pomoc\u00ED programu COMPAS, kter\u00FD byl vytvo\u0159en na pracovi\u0161ti navrhovatele, prototyp bude realizov\u00E1n na obvodech FPGA ATMEL. Pro zlep\u0161en\u00ED diagnostikynavrhovan\u00FDch obvod\u016F bude vytvo\u0159en prost\u0159edek pro urychlen\u00ED simulace poruch pomoc\u00ED model\u016F implementovan\u00FDch na dynamicky rekonfigurovateln\u00FDch obvodech." . . . . "Technology for improving the testability of modern digital circuits"@en . " fault simulation" . . "0"^^ . "2005-01-01+01:00"^^ . "2009-07-02+02:00"^^ . . "2"^^ . . . . . "1"^^ . . "Vvtvo\u0159ena technologie diagnostiky SoC obvodu vyu\u017E\u00EDvaj\u00EDc\u00ED RESPIN architekturu a nov\u00FD komprima\u010Dn\u00ED prost\u0159edek COMPAS. Vyvinut prost\u0159edek pro urychlen\u00ED simulace poruch obvodu pomoc\u00ED modelov\u00E1n\u00ED na FPGA a zrychluj\u00EDc\u00ED simulaci obvodu 10 kr\u00E1t."@cs . " dynamic reconfiguration" . "1QS108040510" . . . " field-programmable gate array" . "testability; fault simulation; field-programmable gate array; dynamic reconfiguration; embedded systems; system on a chip (SoC)"@en . . " embedded systems" . "testability" . . "A new SOC testing methodology was created. It uses the RESPIN architecture and a new test pattern compression tool COMPAS. A tool for ASIC circuit simulation on FPGA was developed. It speeds up the simulation ten times comparing with the software tools"@en . . .