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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F14%3A00224305%21RIV15-GA0-21240___
rdf:type
n10:Vysledek skos:Concept
dcterms:description
The paper describes an ASIC implementation of a linear congruence solver, part of a parallel system for solution of linear equations, and presents synthesis results for three different standard cell libraries. The previous VHDL design was adapted to three ASIC technologies (130 nm, 110 nm, and 55 nm) from two different vendors and the synthesized results were mutually compared. The comparison results were further used to obtain a view of design properties in higher density technologies. The paper describes an ASIC implementation of a linear congruence solver, part of a parallel system for solution of linear equations, and presents synthesis results for three different standard cell libraries. The previous VHDL design was adapted to three ASIC technologies (130 nm, 110 nm, and 55 nm) from two different vendors and the synthesized results were mutually compared. The comparison results were further used to obtain a view of design properties in higher density technologies.
dcterms:title
An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries
skos:prefLabel
An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries
skos:notation
RIV/68407700:21240/14:00224305!RIV15-GA0-21240___
n3:aktivita
n11:P
n3:aktivity
P(GAP103/12/2377)
n3:dodaniDat
n7:2015
n3:domaciTvurceVysledku
Lórencz, Róbert n15:8192553 n15:5573696 n15:7205651
n3:druhVysledku
n14:D
n3:duvernostUdaju
n8:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
2426
n3:idVysledku
RIV/68407700:21240/14:00224305
n3:jazykVysledku
n13:eng
n3:klicovaSlova
system of linear equations; system of linear congruences; residue number system; error-free computation; ASIC; System on Chip
n3:klicoveSlovo
n6:system%20of%20linear%20congruences n6:residue%20number%20system n6:system%20of%20linear%20equations n6:ASIC n6:error-free%20computation n6:System%20on%20Chip
n3:kontrolniKodProRIV
[AA7B26850639]
n3:mistoKonaniAkce
Marseille
n3:mistoVydani
Monterey
n3:nazevZdroje
Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems
n3:obor
n12:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n18:GAP103%2F12%2F2377
n3:rokUplatneniVysledku
n7:2014
n3:tvurceVysledku
Buček, Jiří Zahradnický, Tomáš Kubalík, Pavel Lórencz, Róbert
n3:typAkce
n5:WRD
n3:zahajeniAkce
2014-12-07+01:00
s:numberOfPages
4
n21:doi
10.1109/ICECS.2014.7050083
n19:hasPublisher
IEEE Circuits and Systems Society
n22:isbn
978-1-4799-4243-5
n16:organizacniJednotka
21240