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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F14%3A00224196%21RIV15-GA0-21240___
rdf:type
skos:Concept n13:Vysledek
dcterms:description
This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. A System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system. This paper is focused on hardware error-free solution of dense linear systems using residual arithmetic on a System on Chip Modular System. The designed Modular System uses Residual Processors (RP)s for solving independent linear systems in residue arithmetic and combines RP solutions into solution of the linear system. A System on Chip architecture of the Modular System with several RPs is designed, each with a large memory unit used for data transfer and storage. A Xilinx FPGA architecture with a MicroBlaze processor is used to verify the proposed architecture. The experimental results are obtained for an evaluation FPGA board with Virtex 6 and a 1GiB DDR memory and serve for further theoretical analysis of the system performance for various linear system sizes and the architecture of the system.
dcterms:title
System on Chip Design of a Linear System Solver System on Chip Design of a Linear System Solver
skos:prefLabel
System on Chip Design of a Linear System Solver System on Chip Design of a Linear System Solver
skos:notation
RIV/68407700:21240/14:00224196!RIV15-GA0-21240___
n3:aktivita
n19:P
n3:aktivity
P(GAP103/12/2377)
n3:dodaniDat
n9:2015
n3:domaciTvurceVysledku
n5:8192553 n5:5573696 Lórencz, Róbert n5:7205651
n3:druhVysledku
n12:D
n3:duvernostUdaju
n21:S
n3:entitaPredkladatele
n11:predkladatel
n3:idSjednocenehoVysledku
49141
n3:idVysledku
RIV/68407700:21240/14:00224196
n3:jazykVysledku
n17:eng
n3:klicovaSlova
system of linear equations; system of linear congruences; residue number system; error-free computation; FPGA; System on Chip
n3:klicoveSlovo
n4:system%20of%20linear%20congruences n4:error-free%20computation n4:system%20of%20linear%20equations n4:residue%20number%20system n4:System%20on%20Chip n4:FPGA
n3:kontrolniKodProRIV
[0822D6C80864]
n3:mistoKonaniAkce
Tampere
n3:mistoVydani
Piscataway
n3:nazevZdroje
2014 International Symposium on System-on-Chip Proceedings
n3:obor
n8:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n6:GAP103%2F12%2F2377
n3:rokUplatneniVysledku
n9:2014
n3:tvurceVysledku
Buček, Jiří Lórencz, Róbert Kubalík, Pavel Zahradnický, Tomáš
n3:typAkce
n18:WRD
n3:zahajeniAkce
2014-10-28+01:00
s:numberOfPages
6
n10:doi
10.1109/ISSOC.2014.6972445
n20:hasPublisher
IEEE
n15:isbn
978-1-4799-6889-3
n22:organizacniJednotka
21240