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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F14%3A00219387%21RIV15-MSM-21240___
rdf:type
n13:Vysledek skos:Concept
dcterms:description
We propose a method of the asynchronous sum-of-products (SOP) logic simplification that comprises of minimization and orthogonalization. The method is based on a transformation of the conventional single-rail SOP synchronous logic into the dual-rail asynchronous one operating under so-called modified weak constraints. We formulate and prove the product terms constraint that ensures a correct logic behavior. We have processed the MCNC benchmarks and generated the asynchronous SOP logic. The complexity of the logic obtained is compared with the state-of-the-art representation. Using our approach, we achieve a significant improvement. Copyright 2012 John Wiley & Sons, Ltd. We propose a method of the asynchronous sum-of-products (SOP) logic simplification that comprises of minimization and orthogonalization. The method is based on a transformation of the conventional single-rail SOP synchronous logic into the dual-rail asynchronous one operating under so-called modified weak constraints. We formulate and prove the product terms constraint that ensures a correct logic behavior. We have processed the MCNC benchmarks and generated the asynchronous SOP logic. The complexity of the logic obtained is compared with the state-of-the-art representation. Using our approach, we achieve a significant improvement. Copyright 2012 John Wiley & Sons, Ltd.
dcterms:title
Asynchronous sum-of-products logic minimization and orthogonalization Asynchronous sum-of-products logic minimization and orthogonalization
skos:prefLabel
Asynchronous sum-of-products logic minimization and orthogonalization Asynchronous sum-of-products logic minimization and orthogonalization
skos:notation
RIV/68407700:21240/14:00219387!RIV15-MSM-21240___
n3:aktivita
n9:I n9:Z
n3:aktivity
I, Z(MSM6840770014)
n3:cisloPeriodika
6
n3:dodaniDat
n8:2015
n3:domaciTvurceVysledku
n17:2194937
n3:druhVysledku
n6:J
n3:duvernostUdaju
n19:S
n3:entitaPredkladatele
n11:predkladatel
n3:idSjednocenehoVysledku
4408
n3:idVysledku
RIV/68407700:21240/14:00219387
n3:jazykVysledku
n12:eng
n3:klicovaSlova
logic synthesis; asynchronous logic; sum-of- products logic; minimization
n3:klicoveSlovo
n7:logic%20synthesis n7:minimization n7:sum-of-%20products%20logic n7:asynchronous%20logic
n3:kodStatuVydavatele
US - Spojené státy americké
n3:kontrolniKodProRIV
[7E73D12FF437]
n3:nazevZdroje
International Journal of Circuit Theory and Applications
n3:obor
n4:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
3
n3:rokUplatneniVysledku
n8:2014
n3:svazekPeriodika
42
n3:tvurceVysledku
Suleimanov, R. Fišer, Petr Lemberski, I.
n3:wos
000339503600002
n3:zamer
n15:MSM6840770014
s:issn
0098-9886
s:numberOfPages
10
n16:doi
10.1002/cta.1870
n18:organizacniJednotka
21240