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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F14%3A00219269%21RIV15-GA0-21240___
rdf:type
skos:Concept n19:Vysledek
dcterms:description
The work is focused on design of a Modular System performing error-free solution of dense linear systems using residue arithmetic in Xilinx FPGA. The designed system shall use a set of Residual Processors (RP)s for linear system solution in Residue Number System and reconstruct the set's solution afterwards. The currently proposed system's architecture has a single RP, a large DDR memory used for data transfer in between a PC and the system, and a built-in MicroBlaze processor. Future work will focus on extending the architecture to implement the entire Modular System consisting of multiple RPs and performing the backward transformation from residue representation into the rational number set. The work is focused on design of a Modular System performing error-free solution of dense linear systems using residue arithmetic in Xilinx FPGA. The designed system shall use a set of Residual Processors (RP)s for linear system solution in Residue Number System and reconstruct the set's solution afterwards. The currently proposed system's architecture has a single RP, a large DDR memory used for data transfer in between a PC and the system, and a built-in MicroBlaze processor. Future work will focus on extending the architecture to implement the entire Modular System consisting of multiple RPs and performing the backward transformation from residue representation into the rational number set.
dcterms:title
System Design of an FPGA Linear Solver System Design of an FPGA Linear Solver
skos:prefLabel
System Design of an FPGA Linear Solver System Design of an FPGA Linear Solver
skos:notation
RIV/68407700:21240/14:00219269!RIV15-GA0-21240___
n3:aktivita
n17:P
n3:aktivity
P(GAP103/12/2377)
n3:dodaniDat
n4:2015
n3:domaciTvurceVysledku
n8:5573696 Lórencz, Róbert n8:7205651 n8:8192553
n3:druhVysledku
n18:D
n3:duvernostUdaju
n12:S
n3:entitaPredkladatele
n7:predkladatel
n3:idSjednocenehoVysledku
49090
n3:idVysledku
RIV/68407700:21240/14:00219269
n3:jazykVysledku
n20:eng
n3:klicovaSlova
system of linear equations; residue number system; error-free computation; FPGA
n3:klicoveSlovo
n11:system%20of%20linear%20equations n11:residue%20number%20system n11:error-free%20computation n11:FPGA
n3:kontrolniKodProRIV
[5ACD9C62DC32]
n3:mistoKonaniAkce
Verona
n3:mistoVydani
Linz
n3:nazevZdroje
Proceedings of the Work in Progress Session held in connection with the 40th EUROMICRO Conference on Software Engineering and Advanced Applications and the 17th EUROMICRO Conference on Digital System Design
n3:obor
n16:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n14:GAP103%2F12%2F2377
n3:rokUplatneniVysledku
n4:2014
n3:tvurceVysledku
Lórencz, Róbert Zahradnický, Tomáš Kubalík, Pavel Buček, Jiří
n3:typAkce
n21:WRD
n3:zahajeniAkce
2014-08-27+02:00
s:numberOfPages
2
n15:hasPublisher
Johannes Kepler University
n5:isbn
978-3-902457-40-0
n13:organizacniJednotka
21240