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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F13%3A00209154%21RIV14-GA0-21240___
rdf:type
n10:Vysledek skos:Concept
dcterms:description
Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an FPGA to easily test the functionality of our implementation, then we do the same in ASIC, and finally we compare both implementations together. The experimental FPGA results are obtained for Xilinx Virtex 6, while the ASIC results are obtained from Synopsys tools with a 130 nm standard cell library. Results also present a maximum matrix dimension fitting directly into the FPGA and achieved speed as a function of the dimension. Residual processor (RP) is a dedicated hardware for solution of sets of linear congruences. RPs are parts of a larger modular system for error-free solution of linear equations in residue arithmetic. We present new FPGA and ASIC RP implementations, focusing mainly on their memory units being a bottleneck of the calculation and therefore determining the efficiency of the system. First, we choose an FPGA to easily test the functionality of our implementation, then we do the same in ASIC, and finally we compare both implementations together. The experimental FPGA results are obtained for Xilinx Virtex 6, while the ASIC results are obtained from Synopsys tools with a 130 nm standard cell library. Results also present a maximum matrix dimension fitting directly into the FPGA and achieved speed as a function of the dimension.
dcterms:title
Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver
skos:prefLabel
Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver
skos:notation
RIV/68407700:21240/13:00209154!RIV14-GA0-21240___
n10:predkladatel
n11:orjk%3A21240
n4:aktivita
n23:P
n4:aktivity
P(GAP103/12/2377)
n4:dodaniDat
n21:2014
n4:domaciTvurceVysledku
n14:5573696 n14:7205651 n14:8192553 Lórencz, Róbert
n4:druhVysledku
n17:D
n4:duvernostUdaju
n8:S
n4:entitaPredkladatele
n16:predkladatel
n4:idSjednocenehoVysledku
66209
n4:idVysledku
RIV/68407700:21240/13:00209154
n4:jazykVysledku
n18:eng
n4:klicovaSlova
system of linear equations; residue number system; error-free computation; FPGA; ASIC
n4:klicoveSlovo
n13:FPGA n13:residue%20number%20system n13:ASIC n13:system%20of%20linear%20equations n13:error-free%20computation
n4:kontrolniKodProRIV
[EEA30EBFA004]
n4:mistoKonaniAkce
Santander
n4:mistoVydani
Piscataway
n4:nazevZdroje
Proceedings of 16th Euromicro Conference on Digital System Design
n4:obor
n15:JC
n4:pocetDomacichTvurcuVysledku
4
n4:pocetTvurcuVysledku
4
n4:projekt
n7:GAP103%2F12%2F2377
n4:rokUplatneniVysledku
n21:2013
n4:tvurceVysledku
Kubalík, Pavel Lórencz, Róbert Zahradnický, Tomáš Buček, Jiří
n4:typAkce
n5:WRD
n4:zahajeniAkce
2013-09-04+02:00
s:numberOfPages
4
n12:doi
10.1109/DSD.2013.125
n3:hasPublisher
IEEE Service Center
n22:isbn
978-0-7695-5074-9
n20:organizacniJednotka
21240