This HTML5 document contains 49 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n12http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n14http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F68407700%3A21240%2F12%3A00197211%21RIV14-MSM-21240___/
n22http://localhost/temp/predkladatel/
n20http://purl.org/net/nknouf/ns/bibtex#
n16http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n13http://linked.opendata.cz/resource/domain/vavai/projekt/
n10http://linked.opendata.cz/resource/domain/vavai/subjekt/
n9http://linked.opendata.cz/ontology/domain/vavai/
n8https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n3http://linked.opendata.cz/ontology/domain/vavai/riv/
n15http://bibframe.org/vocab/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n4http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n23http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n6http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n21http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n17http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n19http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F12%3A00197211%21RIV14-MSM-21240___
rdf:type
skos:Concept n9:Vysledek
dcterms:description
The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension. The residual processor is a dedicated hardware for solving sets of linear congruences. It is a part of the modular system for solving sets of linear equations without rounding errors using Residue Number System. We present a new FPGA implementation of the residual processor, focusing mainly on the memory unit that forms a bottleneck of the calculation, and therefore determines the effectivity of the system. FPGA has been chosen, as it allows us to optimally implement the designed architecture depending on the size of the problem. The proposed memory architecture of the modular system is implemented using the internal FPGA block RAM. Experimental results are obtained for the Xilinx Virtex 6 family. Results present the maximum matrix dimension fitting directly into the FPGA, and achieved speed as a function of the dimension.
dcterms:title
Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA
skos:prefLabel
Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA Dedicated Hardware Implementation of a Linear Congruence Solver in FPGA
skos:notation
RIV/68407700:21240/12:00197211!RIV14-MSM-21240___
n9:predkladatel
n10:orjk%3A21240
n3:aktivita
n6:P n6:I
n3:aktivity
I, P(GAP103/12/2377)
n3:dodaniDat
n19:2014
n3:domaciTvurceVysledku
n16:7205651 n16:8192553 n16:5573696 Lórencz, Róbert
n3:druhVysledku
n21:D
n3:duvernostUdaju
n11:S
n3:entitaPredkladatele
n14:predkladatel
n3:idSjednocenehoVysledku
129806
n3:idVysledku
RIV/68407700:21240/12:00197211
n3:jazykVysledku
n23:eng
n3:klicovaSlova
linear systems; system of linear congruences; solver; FPGA
n3:klicoveSlovo
n4:system%20of%20linear%20congruences n4:linear%20systems n4:solver n4:FPGA
n3:kontrolniKodProRIV
[51410F0BC368]
n3:mistoKonaniAkce
Seville
n3:mistoVydani
Monterey
n3:nazevZdroje
The 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012
n3:obor
n17:IN
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n13:GAP103%2F12%2F2377
n3:rokUplatneniVysledku
n19:2012
n3:tvurceVysledku
Kubalík, Pavel Zahradnický, Tomáš Lórencz, Róbert Buček, Jiří
n3:typAkce
n12:WRD
n3:zahajeniAkce
2012-12-09+01:00
s:numberOfPages
4
n15:doi
10.1109/ICECS.2012.6463632
n20:hasPublisher
IEEE Circuits and Systems Society
n8:isbn
978-1-4673-1261-5
n22:organizacniJednotka
21240