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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F11%3A00182599%21RIV12-MSM-21240___
rdf:type
skos:Concept n18:Vysledek
dcterms:description
FPGAs are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one - Stuck-at model - is widely used in many applications and it is not limited to the FPGAs. The second one - Bit-flip model - can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis FPGAs are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one - Stuck-at model - is widely used in many applications and it is not limited to the FPGAs. The second one - Bit-flip model - can affect SRAM cells that are used to configure the internal routing of the FPGA and to set up the behavior of the Look-Up Tables (LUTs). The change of the LUT behavior is the only Bit-flip effect considered in this paper. A fault model analysis has been performed on small example designs in order to find the differences between the fault models. This paper discusses the relevance of using two types of models Stuck-at and Bit-flip with respect to the dependability characteristics Fault Security (FS) and Self-Testing (ST). The fault simulation using both fault models has been performed to verify the analysis
dcterms:title
Fault Models Usability Study for On-line Tested FPGA Fault Models Usability Study for On-line Tested FPGA
skos:prefLabel
Fault Models Usability Study for On-line Tested FPGA Fault Models Usability Study for On-line Tested FPGA
skos:notation
RIV/68407700:21240/11:00182599!RIV12-MSM-21240___
n18:predkladatel
n21:orjk%3A21240
n3:aktivita
n8:Z n8:S n8:P
n3:aktivity
P(GA102/09/1668), S, Z(MSM6840770014)
n3:dodaniDat
n16:2012
n3:domaciTvurceVysledku
n7:6365108 n7:5277973 n7:7140827 n7:7205651
n3:druhVysledku
n22:D
n3:duvernostUdaju
n9:S
n3:entitaPredkladatele
n20:predkladatel
n3:idSjednocenehoVysledku
199424
n3:idVysledku
RIV/68407700:21240/11:00182599
n3:jazykVysledku
n17:eng
n3:klicovaSlova
FPGA; fault model; Bit-flip; Stuck-at; fault simulation
n3:klicoveSlovo
n5:Bit-flip n5:FPGA n5:fault%20model n5:fault%20simulation n5:Stuck-at
n3:kontrolniKodProRIV
[A62CBD96FE1D]
n3:mistoKonaniAkce
Oulu
n3:mistoVydani
Los Alamitos
n3:nazevZdroje
Proceedings of the 14th Euromicro Conference on Digital System Design
n3:obor
n12:JC
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
4
n3:projekt
n10:GA102%2F09%2F1668
n3:rokUplatneniVysledku
n16:2011
n3:tvurceVysledku
Kubalík, Pavel Kohlík, Martin Borecký, Jaroslav Kubátová, Hana
n3:typAkce
n4:WRD
n3:zahajeniAkce
2011-08-31+02:00
n3:zamer
n15:MSM6840770014
s:numberOfPages
4
n11:hasPublisher
IEEE Computer Society Press
n23:isbn
978-0-7695-4494-6
n13:organizacniJednotka
21240