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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F11%3A00179457%21RIV12-MSM-21240___
rdf:type
skos:Concept n21:Vysledek
rdfs:seeAlso
http://www.igi-global.com/embeddedcontent.aspx?PageCode=WGSLd
dcterms:description
The main aim of this chapter is to present the way, how to design fault-tolerant or fail-safe systems in programmable hardware (FPGAs) and therefore to use FPGAs in mission-critical applications, too. RAM based FPGAs are usually taken for unreliable due to high probability of transient faults (SEU) and therefore inapplicable in this area. But FPGAs can be easily reconfigured. Our aim is to utilize appropriate type of FPGA reconfiguration and to combine it with well-known methods for fail-safe and fault-tolerant design (duplex, TMR) including on-line testing methods for fault detection and then startup of the reconfiguration process. Dependability parameters' calculations based on reliability models is integral part of proposed methodology. The trade-off between the requested level of dependability characteristics of a designed system and area overhead with respect to FPGA possible faults is main property and advantage of proposed methodology. The main aim of this chapter is to present the way, how to design fault-tolerant or fail-safe systems in programmable hardware (FPGAs) and therefore to use FPGAs in mission-critical applications, too. RAM based FPGAs are usually taken for unreliable due to high probability of transient faults (SEU) and therefore inapplicable in this area. But FPGAs can be easily reconfigured. Our aim is to utilize appropriate type of FPGA reconfiguration and to combine it with well-known methods for fail-safe and fault-tolerant design (duplex, TMR) including on-line testing methods for fault detection and then startup of the reconfiguration process. Dependability parameters' calculations based on reliability models is integral part of proposed methodology. The trade-off between the requested level of dependability characteristics of a designed system and area overhead with respect to FPGA possible faults is main property and advantage of proposed methodology.
dcterms:title
Fault-tolerant and fail-safe design based on reconfiguration Fault-tolerant and fail-safe design based on reconfiguration
skos:prefLabel
Fault-tolerant and fail-safe design based on reconfiguration Fault-tolerant and fail-safe design based on reconfiguration
skos:notation
RIV/68407700:21240/11:00179457!RIV12-MSM-21240___
n21:predkladatel
n24:orjk%3A21240
n3:aktivita
n14:Z n14:P
n3:aktivity
P(GA102/09/1668), Z(MSM6840770014)
n3:dodaniDat
n12:2012
n3:domaciTvurceVysledku
n19:7205651 n19:7140827
n3:druhVysledku
n22:C
n3:duvernostUdaju
n13:S
n3:entitaPredkladatele
n10:predkladatel
n3:idSjednocenehoVysledku
199428
n3:idVysledku
RIV/68407700:21240/11:00179457
n3:jazykVysledku
n20:eng
n3:klicovaSlova
fault-tolerance; reconfigurability; programmable hardware; on-line testing
n3:klicoveSlovo
n4:programmable%20hardware n4:fault-tolerance n4:on-line%20testing n4:reconfigurability
n3:kontrolniKodProRIV
[73F7DD574A26]
n3:mistoVydani
Hershey, Pennsylvania
n3:nazevZdroje
Design and Test Technology for Dependable Systems-on-Chip
n3:obor
n16:IN
n3:pocetDomacichTvurcuVysledku
2
n3:pocetStranKnihy
314
n3:pocetTvurcuVysledku
2
n3:projekt
n17:GA102%2F09%2F1668
n3:rokUplatneniVysledku
n12:2011
n3:tvurceVysledku
Kubalík, Pavel Kubátová, Hana
n3:zamer
n11:MSM6840770014
s:numberOfPages
20
n9:doi
10.4018/978-1-60960-212-3
n6:hasPublisher
IGI Global
n7:isbn
978-1-60960-212-3
n15:organizacniJednotka
21240