This HTML5 document contains 46 embedded RDF statements represented using HTML+Microdata notation.

The embedded RDF content will be recognized by any processor of HTML5 Microdata.

Namespace Prefixes

PrefixIRI
n11http://linked.opendata.cz/ontology/domain/vavai/riv/typAkce/
dctermshttp://purl.org/dc/terms/
n12http://localhost/temp/predkladatel/
n6http://purl.org/net/nknouf/ns/bibtex#
n10http://linked.opendata.cz/resource/domain/vavai/projekt/
n9http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n14http://linked.opendata.cz/ontology/domain/vavai/
n22http://linked.opendata.cz/resource/domain/vavai/zamer/
n19https://schema.org/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n4http://linked.opendata.cz/ontology/domain/vavai/riv/
n21http://bibframe.org/vocab/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n7http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F68407700%3A21240%2F10%3A00167768%21RIV14-MSM-21240___/
n5http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n23http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n18http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n15http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n20http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n17http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n16http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F10%3A00167768%21RIV14-MSM-21240___
rdf:type
n14:Vysledek skos:Concept
dcterms:description
Recently, it has been shown that synthesis of some circuits is quite difficult for conventional methods. In this paper we present a method of minimization of multi-level logic networks which can solve these difficult circuit instances. The synthesis problem is transformed on the search problem. A search algorithm called Cartesian genetic programming (CGP) is applied to synthesize various difficult circuits. Conventional circuit synthesis usually fails for these difficult circuits; specific synthesis processes must be employed to obtain satisfactory results. We have found that CGP is able to implicitly discover new efficient circuit structures. Thus, it is able to optimize circuits universally, regardless their structure. The circuit optimization by CGP has been found especially efficient when applied to circuits already optimized by a conventional synthesis. The total runtime is reduced, while the result quality is improved further more. Recently, it has been shown that synthesis of some circuits is quite difficult for conventional methods. In this paper we present a method of minimization of multi-level logic networks which can solve these difficult circuit instances. The synthesis problem is transformed on the search problem. A search algorithm called Cartesian genetic programming (CGP) is applied to synthesize various difficult circuits. Conventional circuit synthesis usually fails for these difficult circuits; specific synthesis processes must be employed to obtain satisfactory results. We have found that CGP is able to implicitly discover new efficient circuit structures. Thus, it is able to optimize circuits universally, regardless their structure. The circuit optimization by CGP has been found especially efficient when applied to circuits already optimized by a conventional synthesis. The total runtime is reduced, while the result quality is improved further more.
dcterms:title
On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming
skos:prefLabel
On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming On Logic Synthesis of Conventionally Hard to Synthesize Circuits Using Genetic Programming
skos:notation
RIV/68407700:21240/10:00167768!RIV14-MSM-21240___
n4:aktivita
n18:P n18:Z
n4:aktivity
P(GA102/09/1668), Z(MSM6840770014)
n4:dodaniDat
n16:2014
n4:domaciTvurceVysledku
n9:2194937 n9:2910977
n4:druhVysledku
n17:D
n4:duvernostUdaju
n23:S
n4:entitaPredkladatele
n7:predkladatel
n4:idSjednocenehoVysledku
276742
n4:idVysledku
RIV/68407700:21240/10:00167768
n4:jazykVysledku
n15:eng
n4:klicovaSlova
logic synthesis; multi-level network; genetic programming
n4:klicoveSlovo
n5:genetic%20programming n5:logic%20synthesis n5:multi-level%20network
n4:kontrolniKodProRIV
[C063DB887B48]
n4:mistoKonaniAkce
Vienna
n4:mistoVydani
Piscataway
n4:nazevZdroje
Proc. of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
n4:obor
n20:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
4
n4:projekt
n10:GA102%2F09%2F1668
n4:rokUplatneniVysledku
n16:2010
n4:tvurceVysledku
Fišer, Petr Schmidt, Jan Vašíček, Z. Sekanina, L.
n4:typAkce
n11:WRD
n4:zahajeniAkce
2010-04-14+02:00
n4:zamer
n22:MSM6840770014
s:numberOfPages
6
n21:doi
10.1109/DDECS.2010.5491755
n6:hasPublisher
IEEE
n19:isbn
978-1-4244-6613-9
n12:organizacniJednotka
21240