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Statements

Subject Item
n2:RIV%2F68407700%3A21240%2F09%3A00158715%21RIV11-GA0-21240___
rdf:type
n11:Vysledek skos:Concept
dcterms:description
We propose a novel synthesis method of a dual rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement. We propose a novel synthesis method of a dual rail asynchronous two-level logic of reduced cost. It is based on a model that operates under so called modified weak constraints. The logic is implemented as a minimized AND-OR structure, together with the completion detection logic. We formulated and proved the product term minimization constraint that ensures a correct logic behavior. We processed the MCNC benchmarks and generated asynchronous two-level logic. The implementation complexity was compared with the state-of-the-art approach. Using our approach, we achieved a significant improvement.
dcterms:title
Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes
skos:prefLabel
Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes Multi-Level Implementation of Asynchronous Logic Using Two-Level Nodes
skos:notation
RIV/68407700:21240/09:00158715!RIV11-GA0-21240___
n3:aktivita
n12:Z n12:P
n3:aktivity
P(GA102/09/1668), Z(MSM6840770014)
n3:dodaniDat
n5:2011
n3:domaciTvurceVysledku
n22:2194937
n3:druhVysledku
n18:D
n3:duvernostUdaju
n6:S
n3:entitaPredkladatele
n9:predkladatel
n3:idSjednocenehoVysledku
327982
n3:idVysledku
RIV/68407700:21240/09:00158715
n3:jazykVysledku
n15:eng
n3:klicovaSlova
Asynchronous logic; multi-level implementation
n3:klicoveSlovo
n8:multi-level%20implementation n8:Asynchronous%20logic
n3:kontrolniKodProRIV
[A60769AA5AD0]
n3:mistoKonaniAkce
Gandia Beach, Valencia
n3:mistoVydani
Valencia
n3:nazevZdroje
Proc. of 4th Descrete-Event System Design
n3:obor
n14:JC
n3:pocetDomacichTvurcuVysledku
1
n3:pocetTvurcuVysledku
2
n3:projekt
n7:GA102%2F09%2F1668
n3:rokUplatneniVysledku
n5:2009
n3:tvurceVysledku
Lemberski, I. FiĊĦer, Petr
n3:typAkce
n4:WRD
n3:zahajeniAkce
2009-10-06+02:00
n3:zamer
n20:MSM6840770014
s:numberOfPages
6
n17:hasPublisher
University of Valencia
n16:isbn
978-3-902661-69-2
n19:organizacniJednotka
21240