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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F14%3A00213880%21RIV15-MSM-21230___
rdf:type
n11:Vysledek skos:Concept
rdfs:seeAlso
http://link.springer.com/article/10.1007%2Fs00138-014-0599-0
dcterms:description
We present a complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm. Aside from image analysis, the module embeds a Linux distribution that allows to run programs specifically tailored for particular applications. The module is based on a Virtex-5 FXT FPGA which features powerful configurable logic and an embedded PowerPC processor. We describe the module hardware as well as the custom FPGA image processing cores that implement the algorithm's most computationally expensive process, the interest point detection. The module's overall performance is evaluated and compared to CPU and GPU based solutions. Results show that the embedded module achieves comparable disctinctiveness to the SURF software implementation running in a standard CPU while being faster and consuming significantly less power and space. Thus, it allows to use the SURF algorithm in applications with power and spatial constraints, such as autonomous navigation of small mobile robots. We present a complete hardware and software solution of an FPGA-based computer vision embedded module capable of carrying out SURF image features extraction algorithm. Aside from image analysis, the module embeds a Linux distribution that allows to run programs specifically tailored for particular applications. The module is based on a Virtex-5 FXT FPGA which features powerful configurable logic and an embedded PowerPC processor. We describe the module hardware as well as the custom FPGA image processing cores that implement the algorithm's most computationally expensive process, the interest point detection. The module's overall performance is evaluated and compared to CPU and GPU based solutions. Results show that the embedded module achieves comparable disctinctiveness to the SURF software implementation running in a standard CPU while being faster and consuming significantly less power and space. Thus, it allows to use the SURF algorithm in applications with power and spatial constraints, such as autonomous navigation of small mobile robots.
dcterms:title
FPGA-Based Module for SURF Extraction FPGA-Based Module for SURF Extraction
skos:prefLabel
FPGA-Based Module for SURF Extraction FPGA-Based Module for SURF Extraction
skos:notation
RIV/68407700:21230/14:00213880!RIV15-MSM-21230___
n3:aktivita
n19:P
n3:aktivity
P(7AMB12AR022), P(7E08006)
n3:cisloPeriodika
3
n3:dodaniDat
n13:2015
n3:domaciTvurceVysledku
n8:5603579 n8:3276155 n8:4334175 n8:7211961
n3:druhVysledku
n14:J
n3:duvernostUdaju
n20:S
n3:entitaPredkladatele
n9:predkladatel
n3:idSjednocenehoVysledku
17383
n3:idVysledku
RIV/68407700:21230/14:00213880
n3:jazykVysledku
n15:eng
n3:klicovaSlova
SURF; FPGA; Monocular Navigation; Embedded Systems; Feature Extraction
n3:klicoveSlovo
n5:Embedded%20Systems n5:Feature%20Extraction n5:Monocular%20Navigation n5:SURF n5:FPGA
n3:kodStatuVydavatele
DE - Spolková republika Německo
n3:kontrolniKodProRIV
[B8497302FC69]
n3:nazevZdroje
Machine Vision and Applications
n3:obor
n18:JD
n3:pocetDomacichTvurcuVysledku
4
n3:pocetTvurcuVysledku
5
n3:projekt
n17:7E08006 n17:7AMB12AR022
n3:rokUplatneniVysledku
n13:2014
n3:svazekPeriodika
25
n3:tvurceVysledku
Pedre, S. Přeučil, Libor Šváb, Jan Čížek, Petr Krajník, Tomáš
n3:wos
000333364300017
s:issn
0932-8092
s:numberOfPages
14
n12:doi
10.1007/s00138-014-0599-0
n16:organizacniJednotka
21230