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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F13%3A00212558%21RIV14-MSM-21230___
rdf:type
skos:Concept n8:Vysledek
dcterms:description
Certain classification tasks in computer vision require the classifier response to be computed in every pixel of an image. When combined with large, complex features, it becomes challenging to build such a classifier on a standard PC architecture and achieve real-time performance. We present an FPGA implementation of a car wheel classifier response computation, built as an instantiation of a generic classification system. An interesting optimization problem concerning performance and speed is addressed. Our implementation is running in real-time as a part of a more complex collision mitigation system based on car detection in video data. Certain classification tasks in computer vision require the classifier response to be computed in every pixel of an image. When combined with large, complex features, it becomes challenging to build such a classifier on a standard PC architecture and achieve real-time performance. We present an FPGA implementation of a car wheel classifier response computation, built as an instantiation of a generic classification system. An interesting optimization problem concerning performance and speed is addressed. Our implementation is running in real-time as a part of a more complex collision mitigation system based on car detection in video data.
dcterms:title
FPGA-Accelerated Sliding Window Classifier with Structured Features FPGA-Accelerated Sliding Window Classifier with Structured Features
skos:prefLabel
FPGA-Accelerated Sliding Window Classifier with Structured Features FPGA-Accelerated Sliding Window Classifier with Structured Features
skos:notation
RIV/68407700:21230/13:00212558!RIV14-MSM-21230___
n8:predkladatel
n9:orjk%3A21230
n5:aktivita
n11:P
n5:aktivity
P(7E10037)
n5:dodaniDat
n21:2014
n5:domaciTvurceVysledku
n10:4536975 n10:8483043 n10:8930112
n5:druhVysledku
n18:D
n5:duvernostUdaju
n23:S
n5:entitaPredkladatele
n14:predkladatel
n5:idSjednocenehoVysledku
75619
n5:idVysledku
RIV/68407700:21230/13:00212558
n5:jazykVysledku
n15:eng
n5:klicovaSlova
computer vision; object detection; FPGA
n5:klicoveSlovo
n12:FPGA n12:object%20detection n12:computer%20vision
n5:kontrolniKodProRIV
[ECFF356CB664]
n5:mistoKonaniAkce
Porto
n5:mistoVydani
Piscataway
n5:nazevZdroje
FPL 2013: Proceedings of the 23rd International Conference on Field Programmable Logic and Applications
n5:obor
n6:JD
n5:pocetDomacichTvurcuVysledku
3
n5:pocetTvurcuVysledku
3
n5:projekt
n19:7E10037
n5:rokUplatneniVysledku
n21:2013
n5:tvurceVysledku
Matoušek, Martin Sychrovský, Ondřej Šára, Radim
n5:typAkce
n17:WRD
n5:zahajeniAkce
2013-09-02+02:00
s:numberOfPages
4
n16:doi
10.1109/FPL.2013.6645560
n22:hasPublisher
IEEE
n20:isbn
978-1-4799-0004-6
n4:organizacniJednotka
21230