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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F08%3A03147008%21RIV09-MPO-21230___
rdf:type
skos:Concept n13:Vysledek
dcterms:description
The main aim of our research is to design dependable circuit in FPGA. To make a real dependability model the real effects of injected errors and faults have to be studied. We proposed a hardware fault emulator here. The emulator deals with single-bit change in bitstream. Emulation is performed in user-selected area. Look-Up-Tables, cell interconnection, cell-to-bus connection and routing resources are considered. Other FPGA resources are not considered. Only combinatorial circuits and benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture. The main aim of our research is to design dependable circuit in FPGA. To make a real dependability model the real effects of injected errors and faults have to be studied. We proposed a hardware fault emulator here. The emulator deals with single-bit change in bitstream. Emulation is performed in user-selected area. Look-Up-Tables, cell interconnection, cell-to-bus connection and routing resources are considered. Other FPGA resources are not considered. Only combinatorial circuits and benchmarks were measured due to our knowledge of FPGA resource limitation. All tests were performed on Atmel FPSLIC architecture. Práce se zabývá vlivem jednobitové poruchy v kombinačních obvodech implementovaných v FPGA. Jsou zde popsány modely poruch v FPGA a výsledky z experimentálního měření na emulátoru těchto poruch.
dcterms:title
Experimental emulation of FPGA bitstream faults in combinatorial circuits Experimentální emulace poruch v bitstreamu FPGA v kombinačních obvodech Experimental emulation of FPGA bitstream faults in combinatorial circuits
skos:prefLabel
Experimentální emulace poruch v bitstreamu FPGA v kombinačních obvodech Experimental emulation of FPGA bitstream faults in combinatorial circuits Experimental emulation of FPGA bitstream faults in combinatorial circuits
skos:notation
RIV/68407700:21230/08:03147008!RIV09-MPO-21230___
n3:aktivita
n17:P
n3:aktivity
P(FI-IM4/149)
n3:dodaniDat
n5:2009
n3:domaciTvurceVysledku
n7:7140827 n7:5680182 n7:7205651
n3:druhVysledku
n21:D
n3:duvernostUdaju
n15:S
n3:entitaPredkladatele
n6:predkladatel
n3:idSjednocenehoVysledku
367176
n3:idVysledku
RIV/68407700:21230/08:03147008
n3:jazykVysledku
n4:eng
n3:klicovaSlova
FPGA; FPGA fault models; SEU effect; SEU emulation; bitstream analysis
n3:klicoveSlovo
n16:bitstream%20analysis n16:FPGA%20fault%20models n16:FPGA n16:SEU%20effect n16:SEU%20emulation
n3:kontrolniKodProRIV
[7C93FE5461BC]
n3:mistoKonaniAkce
High Tatras - Stará Lesná
n3:mistoVydani
Košice
n3:nazevZdroje
Proceedings of CSE 2008 International Scientific Conference on Computer Science and Engineering
n3:obor
n11:JC
n3:pocetDomacichTvurcuVysledku
3
n3:pocetTvurcuVysledku
3
n3:projekt
n12:FI-IM4%2F149
n3:rokUplatneniVysledku
n5:2008
n3:tvurceVysledku
Kubalík, Pavel Kubátová, Hana Kvasnička, Jiří
n3:typAkce
n18:WRD
n3:zahajeniAkce
2008-09-24+02:00
s:numberOfPages
8
n20:hasPublisher
Technická univerzita v Košiciach. Fakulta elektrotechniky a informatiky. Katedra počítačov a informatiky
n14:isbn
978-80-8086-092-9
n8:organizacniJednotka
21230