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Namespace Prefixes

PrefixIRI
dctermshttp://purl.org/dc/terms/
n10http://localhost/temp/predkladatel/
n17http://linked.opendata.cz/resource/domain/vavai/riv/tvurce/
n13http://linked.opendata.cz/ontology/domain/vavai/
n15http://linked.opendata.cz/resource/domain/vavai/zamer/
n8http://linked.opendata.cz/resource/domain/vavai/vysledek/RIV%2F68407700%3A21230%2F08%3A03145792%21RIV09-MSM-21230___/
shttp://schema.org/
skoshttp://www.w3.org/2004/02/skos/core#
n4http://linked.opendata.cz/ontology/domain/vavai/riv/
n2http://linked.opendata.cz/resource/domain/vavai/vysledek/
rdfhttp://www.w3.org/1999/02/22-rdf-syntax-ns#
n5http://linked.opendata.cz/ontology/domain/vavai/riv/klicoveSlovo/
n11http://linked.opendata.cz/ontology/domain/vavai/riv/duvernostUdaju/
xsdhhttp://www.w3.org/2001/XMLSchema#
n18http://linked.opendata.cz/ontology/domain/vavai/riv/jazykVysledku/
n14http://linked.opendata.cz/ontology/domain/vavai/riv/aktivita/
n16http://linked.opendata.cz/ontology/domain/vavai/riv/druhVysledku/
n9http://linked.opendata.cz/ontology/domain/vavai/riv/obor/
n7http://reference.data.gov.uk/id/gregorian-year/

Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F08%3A03145792%21RIV09-MSM-21230___
rdf:type
n13:Vysledek skos:Concept
dcterms:description
A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algorithm to synthesize the test pattern generator. In principle, we synthesize a combinational block - the Decoder, transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The Column Matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead. A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algorithm to synthesize the test pattern generator. In principle, we synthesize a combinational block - the Decoder, transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The Column Matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead. A novel test-per-clock built-in self-test (BIST) equipment design method for combinational or full-scan sequential circuits is proposed in this paper. Particularly, the test pattern generator is being designed. The method is based on similar principles as are well known test pattern generator design methods, like bit-fixing and bit-flipping. The novelty comprises in proposing a brand new algorithm to synthesize the test pattern generator. In principle, we synthesize a combinational block - the Decoder, transforming pseudo random code words into deterministic test patterns pre computed by an ATPG tool. The Column Matching algorithm to design the decoder is proposed. Here the maximum of output variables of the decoder is tried to be matched with the decoder inputs, yielding the outputs be implemented as mere wires, thus without any logic. No memory elements are needed to store the test patterns, which reduces the BIST area overhead.
dcterms:title
Column-matching based mixed-mode test pattern generator design technique for BIST Column-matching based mixed-mode test pattern generator design technique for BIST Column-matching based mixed-mode test pattern generator design technique for BIST
skos:prefLabel
Column-matching based mixed-mode test pattern generator design technique for BIST Column-matching based mixed-mode test pattern generator design technique for BIST Column-matching based mixed-mode test pattern generator design technique for BIST
skos:notation
RIV/68407700:21230/08:03145792!RIV09-MSM-21230___
n4:aktivita
n14:Z
n4:aktivity
Z(MSM6840770014)
n4:cisloPeriodika
5-6
n4:dodaniDat
n7:2009
n4:domaciTvurceVysledku
n17:2194937 n17:7140827
n4:druhVysledku
n16:J
n4:duvernostUdaju
n11:S
n4:entitaPredkladatele
n8:predkladatel
n4:idSjednocenehoVysledku
360385
n4:idVysledku
RIV/68407700:21230/08:03145792
n4:jazykVysledku
n18:eng
n4:klicovaSlova
Built-in self-test; Logic design; Mixed-mode testing; Test pattern generator; Weighted random pattern testing
n4:klicoveSlovo
n5:Logic%20design n5:Weighted%20random%20pattern%20testing n5:Test%20pattern%20generator n5:Mixed-mode%20testing n5:Built-in%20self-test
n4:kodStatuVydavatele
NL - Nizozemsko
n4:kontrolniKodProRIV
[08E0B3360F16]
n4:nazevZdroje
Microprocessors and Microsystems
n4:obor
n9:JC
n4:pocetDomacichTvurcuVysledku
2
n4:pocetTvurcuVysledku
2
n4:rokUplatneniVysledku
n7:2008
n4:svazekPeriodika
32
n4:tvurceVysledku
Fišer, Petr Kubátová, Hana
n4:wos
000258992800013
n4:zamer
n15:MSM6840770014
s:issn
0141-9331
s:numberOfPages
11
n10:organizacniJednotka
21230