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Statements

Subject Item
n2:RIV%2F68407700%3A21230%2F08%3A03144365%21RIV09-MSM-21230___
rdf:type
skos:Concept n17:Vysledek
dcterms:description
A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters. A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters. A technique for highly reliable digital design for two FPGAs under a processor control is presented. Two FPGAs are used in a duplex configuration system design, but better dependability parameters are obtained by the combination of totally self-checking blocks based on a parity predictor. Each FPGA can be reconfigured when a SEU fault is detected. This reconfiguration is controlled by a control unit implemented in a processor. Combinational circuit benchmarks have been considered in all our experiments and computations. All our experimental results are obtained from a XILINX FPGA implementation using EDA tools. The dependability model and dependability calculations are presented to document the improved reliability parameters.
dcterms:title
Metodologie spolehliveho navrhu pro systemy na cipu Dependable design technique for system-on-chip Dependable design technique for system-on-chip
skos:prefLabel
Dependable design technique for system-on-chip Dependable design technique for system-on-chip Metodologie spolehliveho navrhu pro systemy na cipu
skos:notation
RIV/68407700:21230/08:03144365!RIV09-MSM-21230___
n3:aktivita
n8:Z
n3:aktivity
Z(MSM6840770014)
n3:cisloPeriodika
54
n3:dodaniDat
n10:2009
n3:domaciTvurceVysledku
n5:7205651 n5:7140827
n3:druhVysledku
n11:J
n3:duvernostUdaju
n7:S
n3:entitaPredkladatele
n18:predkladatel
n3:idSjednocenehoVysledku
362519
n3:idVysledku
RIV/68407700:21230/08:03144365
n3:jazykVysledku
n15:eng
n3:klicovaSlova
Fault security; Self-testing; Totally selfchecking; Reliable digital design; FPGA; Dependability model; Dependability calculations; On-line testing
n3:klicoveSlovo
n14:Fault%20security n14:On-line%20testing n14:Totally%20selfchecking n14:Dependability%20calculations n14:Self-testing n14:Dependability%20model n14:Reliable%20digital%20design n14:FPGA
n3:kodStatuVydavatele
NL - Nizozemsko
n3:kontrolniKodProRIV
[D080CC39C69D]
n3:nazevZdroje
Journal of Systems Architecture
n3:obor
n13:JC
n3:pocetDomacichTvurcuVysledku
2
n3:pocetTvurcuVysledku
2
n3:rokUplatneniVysledku
n10:2008
n3:svazekPeriodika
2008
n3:tvurceVysledku
Kubátová, Hana Kubalík, Pavel
n3:wos
000256705500009
n3:zamer
n12:MSM6840770014
s:issn
1383-7621
s:numberOfPages
13
n16:organizacniJednotka
21230